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We present a method for application of formal techniques like model checking and equivalence checking for validation of the transient response of nonlinear analog circuits. We propose a temporal logic called Ana CTL (computational tree logic for analog circuit verification) which is suitable for specifying properties specific to analog circuits. Th...
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Citations
... Hybrid semi-formal techniques, which combine simulation and formal methods, have been exploited, where the logic model is used to analyze simulation structure. Linear transfer equation is proposed in [5] to describe the two designs for analog system for model checking. The proposed method bases on bi-linear transfer and transfer function is discrete to z domain. ...
... Linear transfer equation is proposed in [5] to describe the two designs for analog system for model checking. The proposed method bases on bi-linear transfer and transfer function is discrete to z domain. ...
This paper proposes a new scalable approach to formal verification (SFV) for AMS SoC designs. Induction rules defined in computer symbolic algebra system Maple are followed to extract representation of property of AMS SoC, constraints solving is performed to formally verify the correctness of the system with respect to its given property. With an AMS description and a set of properties, SMT based model checker is applied to validate if the given system has a certain properties. The proposed methodology is applied on a tunnel diode oscillator. Experimental results for a benchmark and a tunnel diode oscillator demonstrate the effectiveness of the approach. The proposed method is scalable to other AMS system using language VHDL-AMS as description tool.
... While being a significant present research challenge, automated design verification for analog/mixed signal systems is crucial. Several methods have been proposed for formal verification of analog circuits123456789. Most of these methods can be categorized into two categories, equivalence checking and model checking. ...
... As illustrated inFig. 1, most of these existing methods often require the conversion of a high-dimensional continuous state space to a large discrete equivalent so as to apply Boolean-like verification [4][5][7]. The resulting state explosion limits the application of these methods to toy circuits of very low dimensionality. ...
This paper presents a systematic, hierarchical, optimization based semi-formal equivalence checking methodology for large analog/mixed signal systems such as PLLs, ADCs and I/O's. We verify the equivalence between a behavioral model and its electrical implementation over a limited, but highly likely, input space defined as the Constrained Behavioral Input Space. Further, we clearly distinguish between the behavioral and electrical domains and define mappings between the two domains to allow for calculation of deviation between the behavioral and electrical implementation. The verification problem is then formulated as an optimization problem which is solved by interfacing a SQP based optimizer with commercial circuit simulation tools. The proposed methodology is then applied for equivalence checking of a PLL as a test case.
... In [11,12], the authors use an extended temporal logic, AnaCTL (CTL for analog circuit verification), for monitoring the transient behavior of non-linear analog circuits. The transient response of a circuit under all possible input waveforms is represented as an FSM created by means of repeated SPICE simulations, bounding and discretizing the continuous state space of an analog circuit. ...
System-on-chip (SoC) is becoming a core technology in a growing range of consumer and other electronic devices. Cornerstones of SoC designs are analog and mixed signal (AMS) designs, which are integrated circuits required at the interfaces with the real world environment. To respond to certain challenges and due to the limitations of simulation techniques (long simulation runs, inaccurate results, etc.), formal verification of AMS designs emerged as a new area of research. It is a technology based on using computerized algorithms to the mathematical reasoning about the correctness of designs and has been used in the past two decades exclusively for digital design and software verification. This paper provides a review of the state-ofthe-art in AMS formal verification and present advanced approaches that handle continuous as well as discrete-time designs with both linear and non-linear behaviors.
... In [29,30], the authors use an extended temporal logic, AnaCTL (CTL for analog circuit verification), for monitoring the transient behavior of non-linear analog circuits. ...
... One of the approaches to verify AMS circuits proves the correctness of a circuit by finding a finite number of simulation traces that are sufficient to represent all trajectories of the system [23]. Other approaches include verification of formal properties on simulation traces directly [24,25], and generation of a formal model from simulation traces, which can be analyzed using state space exploration techniques [26]. Dastidar et al. generate a finite state machine (FSM) from a set of simulation traces [26]. ...
... Other approaches include verification of formal properties on simulation traces directly [24,25], and generation of a formal model from simulation traces, which can be analyzed using state space exploration techniques [26]. Dastidar et al. generate a finite state machine (FSM) from a set of simulation traces [26]. An acyclic FSM is generated using currents, voltages, and time as state variables. ...
Verification of analog circuits is becoming a bottle-neck for the verification of complex analog/mixed-signal (AMS) circuits. In order to assist functional verification of complex AMS system-on-chips (SoCs), there is a need to represent the transistor-level circuits in the form of abstract models. The ability to represent the analog circuits as behavioral models is necessary, but not sufficient. Though there exist languages like Verilog-AMS and VHDL-AMS for modeling AMS circuits, there is no easy method for generating these models directly from the transistor-level descriptions. This thesis presents an improved method for extracting behavioral models from the simulations of AMS circuits. This method generates labeled Petri net (LPN) models that can be used in the formal verification of circuits, and SystemVerilog models that can be used in the system-level simulations.
Formal verification for analog circuits has grown and is attracting more attention due to the introduction of cyber-physical systems in many technical areas including demanding concepts like autonomous driving. In this chapter, we give an overview of the state of the art including different concepts, and present some new ideas, especially coverage metrics for analog circuit verification. Putting all these concepts together, a methodology is introduced partially answering the question, how a whole system can be formally verified in parallel to the top-down design spanning from system to transistor level. Some results for analog circuits and continuous system-level descriptions are presented, demonstrating the feasibility of the approaches and giving an impression of their capabilities.
Functional errors in analog portion of mixed signal circuits become more severe and improvements in verification methods are increasingly important. Current verification methods fall into two categories, simulation-based verification and formal verification (Barke et al. [1]), focusing on verifying analog circuit function/performance. This paper proposes a novel approach verifying analog circuit design using causal reasoning. Causal reasoning is the inductive reasoning process to create a new design. The flow begins with mining the causal reasoning steps (design plan) that produced the circuit, including starting ideas, design step sequence, and their justifications (Jiao et al., 2015 [2]). Then, topological features corresponding to the starting ideas and design step sequence are verified individually by replacing the related devices with ideal behavior model. Performance is evaluated through Cadence Spectre simulation. Comparison with new circuit performance reveals incorrect functional issues and/or performance potentials for improvement. They are negative causes of certain starting ideas or design steps, which might have been omitted during the design process. The paper discusses three operational amplifier designs realized in 0.2-μm CMOS technology to illustrate the verification approach.
The acceptance criteria for analog designs are traditionally defined in terms of real-valued features defined over behavioral responses. For example, rise time, peak overshoot, and settling time are features of the response of a second-order system under a step input. Designers of analog and mixed-signal (AMS) designs typically like to see whether the relevant features lie within their specified ranges, and if so, by what margin. Assertions are capable of capturing the acceptance criteria, but they do not help in evaluating how well (or by what margin) the design satisfies the specification. We introduce the notion of Feature Indented Assertions (FIAs) for overlaying the definition of real-valued features over the syntactic fabric of AMS assertions. In this paper, we present the formal syntax and semantics of our language, FIA, and demonstrate its ability to capture a wide variety of AMS features. We present our dynamic feature evaluation tool that plugs into standard AMS simulators through Verilog Procedural Interfaces and evaluates features over simulation. At the heart of this tool, we have our interval arithmetic-based algorithm for monitoring features over continuous time and value domains. This algorithm is presented with corresponding proofs of correctness and with results over industrial testcases.
