Virtex-4 FPGA logic slice: LUTs, RAM... 

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... reconfigurable, DNA, RNA, Smith- Waterman, Cray, FASTA, XD1, Virtex, OpenFPGA This paper describes Field-Programmable Gate Arrays (FPGAs), several tools used to program them and how 100X speedup was achieved for a science application. Remarkable innovations in computer technology [1-2] are fulfilling NASA future projections [3] for faster science and engineering computations. One innovation in the forefront is to harness FPGAs to accelerate High-Performance Computing (HPC) applications by one or more orders of magnitude over traditional microprocessors. FPGAs were invented in 1984 by Ross Freeman, co-founder of Xilinx Inc. FPGAs are extremely flexible and dominated by interconnections to thousands of embedded functions ( Fig. 1. left) like adders, multipliers, memory, and logic slices ( Fig. 2 ). They perform high-speed computations and communications (e.g., Hypertransport) in parallel via digital logic: LookUp Tables (LUTs), Registers, RAM, etc. Unlike “fixed” microprocessors, FPGA’s are reconfigurable “on the fly” by users in the “field”, thus, “field programmable”. The Virtex-4 is available with one or more PowerPC (PPC) processors on the chip ( Fig 1 . right). The rapidly growing (15-20%/year) $2B FPGA market (focused on the high-volume communications) is dominated by Xilinx and Altera. Aerospace and High-Performance Embedded Computing (HPEC) users are rapidly expanding their FPGA use. Although HPC sales (< 1%) are small, FPGA designers are open to HPC requirements for their next generation designs. : FPGA layout is extremely regular compared to microprocessors, simplifying fabrication, and allowing FPGAs to be among the first to reduce feature sizes (90nm => 65nm => 45nm). For space and flight use, this regularity and triply-redundant code, limits radiation damage (i.e. NASA Mars Rovers). At each clock cycle, FPGA algorithms (when coded to maximize the number of parallel operations) use nearly 100% of their silicon, compared to less efficient microprocessors which use < 2% of their silicon (while drawing 10x FPGA power to perform only one or two operations). Figure 3 shows several key FPGA characteristics. Unlike microprocessors, FPGAs continue to advance at Moore’s Law rate and have far to go before reaching logic cell and speed limits ( Fig. 3 ., left). FPGA clock speeds (often 100- 200 MHz) have far to go before facing heating issues that drove microprocessors to multi-core chips with reduced clock speeds. When FPGA applications are programmed to maximize parallelism, their computation speed far exceeds that of microprocessors ( Fig. 3 ., right). Being high-speed communications devices, the memory and IO bandwidths also significantly exceed those of microprocessors ( Fig. 3 ). : As FPGAs were developed by logic designers, they are traditionally programmed using circuit design languages such as VHDL and Verilog. These languages require the knowledge and training of a logic designer, take months to learn and far longer to code efficiently. Even once this skill is acquired, VHDL or Verilog coding is extremely arduous, taking months to develop early prototypes and often years to perfect and optimize. FPGA code development, unlike HPC compilers, is greatly slowed by the additional lengthy steps required to synthesize, place and route the circuit. Once the time is taken to code applications in VHDL, its FPGA performance is excellent. In particular, applications using basic integer or logic operations (compare, add, multiply) such as DNA sequence comparisons, cryptography or chess logic, run extremely well on FPGAs. As floating point and double-precision applications rapidly exhausted the number of slices available on early FPGAs, they were often avoided for high-precision calculations. However, this situation has changed for current Xilinx FPGAs (Virtex-4 and Virtex-5) which have sufficient logic to fit about 80 64-bit multiply units [ 2 ]. While early FPGAs had sufficient capability to be well suited for special-purpose HPEC, their use for general- purpose HPC was initially restricted to a first-generation of low-end reconfigurable supercomputers. (i.e. Starbridge Systems, SRC, Cray XD1). The lack of high-speed IO and infrastructure (compilers, libraries) to support general- purpose supercomputer applications, including legacy codes are typical of this early generation. However, this situation is rapidly changing with the latest generation of reconfigurable supercomputers and the FPGAs they use. DRC Computer, Xtreme Data and Xilinx in collaboration with Intel provide modules with the latest FPGAs which fit in microprocessor sockets and use the same high-speed communications link. Cray selected DRC’s module, Fig. 4 , to accelerate its XT line of supercomputers. Accelerating HPC applications is so critical that many alternatives have entered the marketplace. Even though many legacy physics-based codes are written in sequential Fortran over 30 years ago, they have remarkably survived several HPC generations: vector (via compilers), parallel (via MPI, OpenMP) and now the first stages of multi-core microprocessors. Some surmise they may suffer severe performance degradation or even require significant rewrites to fully exploit 8 or more cores/chip. Major chip vendors (Intel and AMD) have vigorous efforts to accommodate accelerators, with their primary focus on FPGAs as a way to regain performance. As multi-core microprocessors face looming power, cooling, size and IO challenges, FPGAs are increasingly attractive. Accelerator Options: Three other accelerator options are available to HPC architects: Cell (IBM), Graphics (GPUs) and Array (ClearSpeed) processors. Like FPGAs, Cell and GPUs have vast commercial markets (video games and graphics) driving down costs, promoting competition and stimulating advances making them increasingly attractive to HPC. Array processors, however, are custom devices requiring amortization over relatively few users. GPUs require significant power/cooling and have complex programming and data precision issues to solve before they can enter the HPC market. Coding the 8+1 Cell processors is likely to be considerably more difficult than programming FPGAs in VHDL or Verilog, which already has a large user base. As FPGA hardware advances, tools/ software are simplifying their use for HPC: Viva, MitrionC, & Xilinx’s CHiMPS (all discussed later) as well as DSPlogic, ImpulseC, Celoxica, Aldec, and, others. The authors are testing CHiMPS for HPC ...