Figure 2 - uploaded by Ahmed Jerraya
Content may be subject to copyright.
![Videophone CODEC Architecture The purpose of the Motion Estimator is to determine the motion vector of a moving part of a picture by comparison of the current frame and the previous one, stored in the VRAM ((gure 2). According to the H261 1 CCITT 2 algorithm 18], a picture is cut into 99 macro-blocks to allow parallelism between the diierent operators. The search window of the motion vector is limited to scan 16 horizontal vectors and 16 vertical vectors in the previous picture. The Motion Estimator calculates the "distance" or distortion between the current macro-block and the 256 existing possible positions of the macro-blocks in the search window. The function of the Motion Estimator is mainly a DFD operation. However, it also involves a quite complex Control Flow. Indeed, because of the distributed architecture of the CODEC, it includes two local memories that are lled using a complex external protocol. Besides it communicates with the MSQ (sequencing the overall operations of the chip) through a well deened protocol.](profile/Ahmed-Jerraya/publication/3641524/figure/fig1/AS:669988532785153@1536749122263/Videophone-CODEC-Architecture-The-purpose-of-the-Motion-Estimator-is-to-determine-the.png)
Videophone CODEC Architecture The purpose of the Motion Estimator is to determine the motion vector of a moving part of a picture by comparison of the current frame and the previous one, stored in the VRAM ((gure 2). According to the H261 1 CCITT 2 algorithm 18], a picture is cut into 99 macro-blocks to allow parallelism between the diierent operators. The search window of the motion vector is limited to scan 16 horizontal vectors and 16 vertical vectors in the previous picture. The Motion Estimator calculates the "distance" or distortion between the current macro-block and the 256 existing possible positions of the macro-blocks in the search window. The function of the Motion Estimator is mainly a DFD operation. However, it also involves a quite complex Control Flow. Indeed, because of the distributed architecture of the CODEC, it includes two local memories that are lled using a complex external protocol. Besides it communicates with the MSQ (sequencing the overall operations of the chip) through a well deened protocol.
Source publication
This paper presents the design of a Videophone Coder-Decoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (complex communication protocol) with a Data Flow Dominated part (high throughput computations) makes this circuit difficult to be synthesized by a single HLS tool. The combinat...
Similar publications
FPGAs excel in low power and high throughput computations, but they are challenging to program. Traditionally, developers rely on hardware description languages like Verilog or VHDL to specify the hardware behavior at the register-transfer level. High-Level Synthesis (HLS) raises the level of abstraction, but still requires FPGA design knowledge. P...
FPGAs excel in low power and high throughput computations, but they are challenging to program. Traditionally, developers rely on hardware description languages like Verilog or VHDL to specify the hardware behavior at the register-transfer level. High-Level Synthesis (HLS) raises the level of abstraction, but still requires FPGA design knowledge. P...
Citations
... It offers an object-oriented modeling environment, where all objects can be modeled regardless of their future implementation as digital or analog hardware or software. Most work on hardware and software co-design focus on the synthesis of a dedicated hardware or of a dedicated instruction set processor [1] [6] [9] [10] [11] [12]. On the other hand, in S 3 E 2 S one focus on a multi-processor paradigm. ...
This paper presents the synthesis technique available in S 3 E 2 S, a CAD environment to specify, simulate, and synthesize electronic systems that can be modeled as a combination of analog parts, digital hardware, and software. S 3 E 2 S is based on a distributed, object-oriented system model, where abstract objects are initially used to express complex behavior and may be lat-er refined into digital or analog hardware and software. Finally, system synthesis is targeted to a set of complex processors, which can be either custom designed or off-the-shelf components. The environment selects processors that best match the desired application by analyzing processor and application characteristics. The paper explains the architecture selection process with some examples.
Behavioral synthesis bridges the gap between abstract specifications and concrete hardware implementations. The behavioral synthesis problem consists of mapping a largely incompletely defined behavior into a well-defined hardware implementation with fixed sequential behavior. This paper presents an overview of the main algorithms and issues related to behavioral synthesis and analyzes the pros and cons of each technique. It also discusses the place for behavioral synthesis in the overall digital design methodology and the main advantages and drawbacks of its use
This paper presents the system synthesis techniques available in S <sup>3</sup>E<sup>2</sup>S, a CAD environment for the specification, simulation, and synthesis of embedded electronic systems that can be modeled as a combination of analog parts, digital hardware, and software. S<sup>3</sup>E<sup>2</sup>S is based on a distributed, object-oriented system model, where objects are initially modeled by their abstract behavior and may be later refined into digital or analog hardware and software. System synthesis is targeted to a multiprocessor platform. Each processor, either a custom-designed one or an off-the-shelf component, can have a specialized behavior like signal processing or control processing. The environment selects processors that best match the desired application by analyzing and comparing processor and application characteristics. The paper illustrates the architecture selection process with concrete examples
Complex consumer products with multiple functions on a single chip
demand new design and verification methods for interfunctioning hardware
and software components. The authors' new techniques address this need
The paper proposes a new model for verification and high level synthesis (re)using complex units like co-processors. The model is called FSMC (FSM with Co-processors) and is an extension of the FSMD model (FSM with Data path). The verification method is based on model checking. It permits to analyze the properties and consistency of the whole system and, particularly, the correct (re)use of design blocks. 1 Introduction One of the ways to increase designer productivity is the re-use of a previously validated design or a part of design. Design re-use is more efficient at a higher level of abstraction. The general methodology for component re-use applied to high level synthesis is considered in the previous works [KDJ94], [KDJ95]. The synthesis task becomes relatively simple: to put together a small number of large units. However, the main difficulty is to assure the correct behavior of an entire design. The long term goal of this work is a formal verification of a result of high level ...
