Figure 8 - uploaded by Md Nasim Afroj Taj
Content may be subject to copyright.
![Verilog Timing Diagram](profile/Md-Nasim-Afroj-Taj-2/publication/355348268/figure/fig1/AS:1079557918601223@1634398073739/Verilog-Timing-Diagram.png)
Verilog Timing Diagram
Source publication
This was our project in level 3 term 2 for the course EEE 304 titled, Digital Electronics Laboratory. In this project, we proposed a simple hexadecimal password-based lock system.
Similar publications
Digital Electronics Laboratory Microcontroller Based Digital Calculator Using Proteus