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Venn diagram showing quantifiability (green dashes) and other correctness conditions within the bounds of Serializability
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Architectural imperatives due to the slowing of Moore’s Law, the broad acceptance of relaxed semantics and the O(n!) worst case verification complexity of generating sequential histories motivate a new approach to concurrent correctness. Desiderata for a new correctness condition are that it be independent of sequential histories, compositional, fl...
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GenMC is a state-of-the-art stateless model checker that can verify safety properties of concurrent C/C++ programs under a wide range of memory consistency models, such as SC, TSO, RC11, and IMM.
In this paper, we improve the performance and usability of GenMC : we provide a probabilistic estimate of the expected verification cost, we automate the...
