Fig 5 - uploaded by Xinfei Guo
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VTC curves under different supply voltages for a 1xnm FinFET inverter (PMOS and NMOS are sized equally).
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It has been almost a decade since FinFET devices were introduced to full production; they allowed scaling below 20 nm, thus helping to extend Moore's law by a precious decade with another decade likely in the future when scaling to 5 nm and below. Due to superior electrical parameters and unique structure, these 3-D transistors offer significant pe...
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Citations
... The quantum mechanical effects and quantum transport mobility models have been used to analyze the electrostatic behavior of CMOS inverters [46][47][48]. The net dopant concentration (conc.) of the CMOS inverter is shown in Fig. 11. ...
... In Fig. 12 V out and power factor are shown as a function of time with different fin heights. It is seen that a larger power is obtained at a higher fin height because of the large current; hence it provides maximum power [48]. At fin height 40 nm, the inverter provides optimum response such as power and V out . ...
Stress engineering is one of the best techniques to enhance the potential of a device. In the first phase of this work, the impact of stress on the physical and electrical performance of FinFET based inverter is investigated using 2D and 1D stress mapping techniques. Electrons and holes mobility enhancements are presented in the sidewall fins of <100> and < 110> direction respectively, by resulting tensile stress in n-FinFET and compressive stress in p-FinFET. According to the sidewall orientation (<100 > or < 110>), the amount of mobility enhancement of both the electrons and holes are resulting in more than 100% (>100%) and less than 25% (<25%) respectively. In the second phase, Design Technique Co-Optimization (DTCO) method is approached in inverter standard cells generation to enable the VLSI digital system design flow based on standard cells using FinFET. FinFET-based inverters at 7 nm technology nodes is designed using the GTS TCAD framework. The optimal electrical characteristics such as current density, throughput delay, average power dissipation, and switching energy are presented with optimal design.
... The gate capacitance C ox depends on relative dielectric constant of dielectric material (2) where K is the dielectric constant of the material (K = , is equal to 8.85 × 10 -12 F/m), A is the capacitor gate area in cm 2 , t ox is the thickness of the dielectric layer, ε ox is the oxide relative permittivity. ...
... Also, the write and read operations occur only in one cell, which, as mentioned, in addition to reducing errors, it reduces power consumption. P-FET access have been used to reduce static power, because in FinFET technology P-FET have less leakage current than N-FET [20,22], that by increases the height of the stack, this leakage of the transistors decreases even more [20,23]. In the proposed design for the reading path, the bit-line is separated from the power supply by three P-type transistors and in the writing path by two P-type transistors. ...
... For hold-static-noise-margin (HSNM) due to the use of FinFET technology and almost equal current of P-FET and N-FET in crosscoupled inverters [23], HSNM is obtained for almost all designs close to each other. However, in the SBL9T design, due to disconnecting the ground of the inverters in standby state have much lower HSNM as compared to other designs, also, the TRD9T design due to the use of NFET between the two inverters and its threshold drop, slightly reduces the noise margin. ...
... In general, major leakage currents can be divided into three parts, which include sub-threshold current, gate leakage current and junction leakage current [16,41]. In FinFETs, due to the narrow and high structure of Fins, the body leakage is very lower than MOSFET and the body effects are much less involved [23], so writing and calculating the junction current that is related to the body effect is omitted. In FinFET, due to more gate coverage on the channel, gate leakage can be increased as compared to MOSFET [23]. ...
In this paper, a robust sub-threshold 13T-SRAM cell is designed, which in addition to reducing power and energy consumption can show high reliability and have the least error at low voltages. This cell is completely free from the half-select issue, which is one of the important factors in increasing power and decreasing reliability, especially at low voltage levels for SRAM arrays. It is designed without the need of write-bit-line, which according to the proposed techniques reduces the power consumption and significantly improves the write margin, also the lack of this bit-line in the memory array can reduce the total power consumption. The used bit-line only performs for read operation, therefore it has least activity. Also, an 8Kb memory array is proposed to be able to perform various operations with less complexity, simpler logic and lower power consumption by proposing several techniques on peripheral circuits. All obtained noise margins according to proposed techniques have the highest values among the compared cells. The average power and PDP of the cell are less than all the compared designs, so that the average power and presented FoM has been improved by 6.83% and 18.46% respectively as compared to the best value of other designs.
... According to the 2016 road map ITRS 2.0, FinFET will be the dominant future transistor in CMOS technology because of its ability to continue scaling down to 5 nm node technology and beyond [6], because its finshaped channel, which tends to superior gate control, then enables many improvements of short channel effects in planner MOSFET, like improved subthreshold slope and higher ION/IOFF ratio [7,8]. The perfect gate design with low OFF state leakage current tends to adoption of FinFET for high-volume ICs production with 22 nm node technology generation [9]. ...
... Some of these problems are increased leakage current and process variation effect [1,2]. This problem is exacerbated for Planar MOSFETs in dimensions approximately below 65 nm [15,18,19]. As one of the solutions to this problem, fabrication of Planar MOSFET as the SOI (silicon on insulator) and using high-k materials instead of the oxide layer under the gate and making the layer thinner [18,20], so that it can have better control over the channel and the substrate leakage can be improved [18,21]. ...
... This problem is exacerbated for Planar MOSFETs in dimensions approximately below 65 nm [15,18,19]. As one of the solutions to this problem, fabrication of Planar MOSFET as the SOI (silicon on insulator) and using high-k materials instead of the oxide layer under the gate and making the layer thinner [18,20], so that it can have better control over the channel and the substrate leakage can be improved [18,21]. However, it should be noted that the thinning of the gate oxide layer, increases the GIDL (gate-induced drain leakage) [18,20], in addition to being costly. ...
... This problem is exacerbated for Planar MOSFETs in dimensions approximately below 65 nm [15,18,19]. As one of the solutions to this problem, fabrication of Planar MOSFET as the SOI (silicon on insulator) and using high-k materials instead of the oxide layer under the gate and making the layer thinner [18,20], so that it can have better control over the channel and the substrate leakage can be improved [18,21]. However, it should be noted that the thinning of the gate oxide layer, increases the GIDL (gate-induced drain leakage) [18,20], in addition to being costly. ...
In this paper, a robust 12T-SRAM memory cell at sub-threshold voltage is designed to reduce power consumption for low power applications, that in addition to reducing power consumption can perform well at high frequencies and remain stable. For the write operation, a new method has been used that removes the write bit line and uses the supply voltage in each cell for this operation and only by applying control signals. Also, the embedded bit line is used only for read operations and reduces the activity of the bit line, and due to being floating and the way of writing, eliminates the Precharge and Write Driver circuits, so, part of the power and area consumption has been reduced. According to the techniques used, the write and read noise margin is significantly improved and the write operation become easier to perform. Also due to the existence of a separate path for the read operation, RSNM is equaled to the HSNM. The average cell power at the frequency of 100MHz for low power applications and 0.2V supply voltage, as compared to the best previous designs, has been improved by 34.9% and the leakage power of the hold state has been reduced by 27.6% and PDP has been improved by more than 35.2%, further, the maximum operating frequency of the cell has been increased by 39.1%, while it operates with the sub-threshold voltage of 0.2V to the frequency of 2.173GHz.
... FinFET had its origin when the Defense Advanced Research Projects Agency (DARPA) was keen to fund the research possibilities of replacing the planar transistors. It was impossible to scale transistors below 28 nm, but FinFET brought a revolution by decreasing the transistor size down to 14 nm [48]. They were introduced by a team from the University of California at Berkeley led by Chenming Hu in 1990 [6]. ...
... On the other hand, for SG FinFET, the channel is controlled jointly by both gates similar to conventional MOSFETs. This provides higher I ON and I OFF in contrast to IG FinFET [2], [48], [50]. But the challenges faced by IG FinFETs are not so easily resolved. ...
... SoI substrates continue to be a better alternative when it comes to device fabrication. In 2004, Hook et al. [51] predicted the superiority of SoI wafers over the bulk ones, in terms of the key parameters like mobility, reliability, low-temperature operations, and ability to survive in harsh environments [2], [48]. ...
In the contemporary era of Internet-of-Things, there is an extensive search for competent devices which can operate at ultra-low voltage supply. Due to the restriction of power dissipation, a reduced sub-threshold swing based device appears to be the perfect solution for efficient computation. To counteract this issue, Negative Capacitance Fin field-effect transistors (NC-FinFETs) came up as the next generation platform to withstand the aggressive scaling of transistors. The ease of fabrication, process-integration, higher current driving capability and ability to tailor the short channel effects (SCEs), are some of the potential advantages offered by NC-FinFETs, that attracted the attention of the researchers worldwide. The following review emphasizes about how this new state-of-art technology, supports the persistence of Moore’s law and addresses the ultimate limitation of Boltzmann tyranny, by offering a sub-threshold slope (SS) below 60 mV/decade. The article primarily focuses on two parts-i) the theoretical background of negative capacitance effect and FinFET devices and ii) the recent progress done in the field of NC-FinFETs. It also highlights about the crucial areas that need to be upgraded, to mitigate the challenges faced by this technology and the future prospects of such devices.
... The voltage transfer characteristics curves (VTC) have been analyzed for different fin heights shown in Figure 9. From Figure 9, the VTC curves have been shown for different fin heights of the inverters. From the characteristics, we observed the VTC slope at fin height 40 nm shows a better response than 20 nm [17]. The VTC curve is steeper at larger fin height, i.e., at 40 nm, which provides a better relationship between Vout and Vin of the inverter. ...
... The cell height is a significant parameter, but unfortunately, it is not under the control of the designer. For smaller Fin heights are more flexible but results in more area Guo et al. [24]. The increase in cell height will result in high capacitance at nodes, which affects the transient response Villacorta et al. [23]. ...
... It has a regular structure, and uses a common 3transistor topology for producing each output. Moreover, with the use of FinFETs, additional properties may be enabled in back-end design due to 3D gate structures Guo et al. [24]. As the channel of the FinFETs is covered completely by the gate, it can control the current through the Fig. 1. (a). ...
Conventional CMOS has become successful logic for most digital VLSI circuits and a good candidate in terms of power dissipation. But due to its dual nature, more transistors are required and are not suitable as the technology is scaled down. This paper proposes a Double Gate (DG) FinFET based 4-1, 8-1, 16-1 multiplexer (DFMs) with a reduced number of transistors catering to the needs of low-power dissipation and high speed. For designing the proposed 4-1 DG-FinFET digital multiplexer (DFM) circuit requires only 16 FinFETs. Compared to the CMOS multiplexer circuit’s conventional architecture, the proposed 4-1 DFM design uses a single pull-up FinFET in its first stage, and the second stage has only 4 FinFETs. The DFM circuit design is extended to 8-1 and 16-1 targeting to reduce transistor count, delay, and power dissipation. Extensive simulations are done at a 22nm technology node using Eldo software of Mentor Graphics. With the simulated results of proposed and conventional CMOS designs at different supply voltages and load capacitances on the 22nm technology node, the proposed DFM multiplexers’ power-delay product is better. For 1 GHz of frequency and the least feasible supply voltage of 0.8V, the proposed digital multiplexer attains a 10% reduction in power dissipation and a 6% reduction in delay. Including inverters in the designs, the transistor count is also less compared to the conventional static multiplexer.
... Memristor has been used for programmable filters, which have tunable cut-off frequencies [7]. The basic features of FinFET are studied, and its advantages over CMOS transistor are also highlighted in [8]. ...
There are limitations in CMOS transistor as the technology scales down. The problem of short channel effects (SCE) has become dominant, which causes the malfunction and failure of CMOS circuits. Various devices are proposed to continue extending Moore’s law and the roadmap in semiconductor industry. Memristor is a two terminal passive device, which has proven to be compatible with MOSFET microfabrication processes and also offers some distinctive features. It is a nano-dimensional device, so it saves a lot of die area and consumes less power. Similarly, FinFET structure has aided in better electrostatic control of transistor channel. The leakage current and power are reduced, thus, it shows better performance than MOS transistor. FinFET exhibits temperature effect inversion (TEI) because its 𝐈𝐎𝐍 increases even at the superthreshold region. The integration of graphene nanoribbon (GNR) FET into IC design has shown a lot of improvements in terms of speed and power. In this work, we present the characteristics of GNRFET and design an inverter circuit using Cadence/Spectre. Following this, a three-stage ring oscillator (RO) is designed, and the results show that its center frequency is 30.2 GHz with a phase noise of -125.2dBc/Hz. In addition, it consumes 0.15 mW power, which makes it suitable for high frequency and low power applications. More so, the RO has a very good phase noise performance.
... According to the ITRS 2.0 roadmap (2016), FinFET will be the dominant transistor of the future in CMOS technology due to its ability to continue scaling down to 5 nm node technology and beyond [6], because its finshaped channel, which tends to have superior gate control, then allows to significantly improve short channel effects in planar MOSFETs, such as subthreshold slope and higher ION/IOFF ratio [7,8]. The perfect gate design with low OFF-state leakage current promotes the adoption of FinFETs for high-volume IC production with 22 nm node technology generation [9]. ...
