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As the technology node size decreases, the number of static random-access memory (SRAM) cells on a single word line increases. The coupling capacitance will increase with the increase of the load of word line, which reduces the performance of SRAM, more obvious in the SRAM signal delay and the SRAM power usage. The main purpose of this study is to...
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... Consequently, the size of SRAM circuits has decreased significantly [6]. As a result, power dissipation has become a growing concern while designing SRAMs in nanometer technology [7]. The two major operations, read and write, drive the performance of an SRAM cell and, therefore, the factors taken into consideration for design are the dynamic power consumption and latency during these two operations [8]. ...
An innovative 8 transistor (8T) static random access memory (SRAM) architecture with a simple and reliable read operation is presented in this study. LTspice software is used to implement the suggested topology in the 16nm predictive technology model (PTM). Investigations into and comparisons with conventional 6T, 8T, 9T, and 10T SRAM cells have been made regarding read and write operations' delay and power consumption as well as power delay product (PDP). The simulation outcomes show that the suggested design offers the fastest read operation and PDP optimization overall. Compared to the current 6T and 9T topologies, the noise margin is also enhanced. Finally, the comparison of the figure of merit (FoM) indicates the best efficiency of the proposed design.
... The initial voltage was set to 0 V, and the simulation was performed over a 1-ns transient period. Figure 11 shows the 6T-SRAM simulation results for the hold, read, and write operation margins [26]. In the 6T-SRAM simulation, the device width was set to 1:a:b in order to account for the static noise margin (SNM) [27]. ...
In this paper, we present an artificial neural network (ANN)-based compact model to evaluate the characteristics of a nanosheet field-effect transistor (NSFET), which has been highlighted as a next-generation nano-device. To extract data reflecting the accurate physical characteristics of NSFETs, the Sentaurus TCAD (technology computer-aided design) simulator was used. The proposed ANN model accurately and efficiently predicts currents and capacitances of devices using the five proposed key geometric parameters and two voltage biases. A variety of experiments were carried out in order to create a powerful ANN-based compact model using a large amount of data up to the sub-3-nm node. In addition, the activation function, physics-augmented loss function, ANN structure, and preprocessing methods were used for effective and efficient ANN learning. The proposed model was implemented in Verilog-A. Both a global device model and a single-device model were developed, and their accuracy and speed were compared to those of the existing compact model. The proposed ANN-based compact model simulates device characteristics and circuit performances with high accuracy and speed. This is the first time that a machine learning (ML)-based compact model has been demonstrated to be several times faster than the existing compact model.
... SNM is dependent on supply voltage, temperature, Cell Ratio (CR) and Pull-up Ratio (PR) [29]. Stability of the SRAM cell is examined by sketching butterfly curve and then length of maximum possible square is observed that can be embedded in it, that is the value of SNM [30][31]. Figs. 12, 13 and 14 show the SNM plot for SRAM Cell in hold mode, read mode and write operation, respectively. ...
With aggressive scaling of device feature size, performance of conventional MOS SRAM is affected and reliability, leakage power dissipation, and testing related issues arise due to short channel effects. So CNTFET device is promising and ideal candidate to replace existing MOS technology because of its excellent performance and high thermal stability. In this paper design and analysis of CNTFET SRAM cell, Reverse Logic enabled SRAM (RL-SRAM) and RL-SRAM with body bias is presented at 32 nm using Vdd 0.7 V. Adiabatic technique is incorporated in SRAM cell that uses reversible logic, plays an important role to reduce power consumption by recycling the energy stored at node capacitance instead of dissipating in form of heat. By incorporating of reversible logic with SRAM, 60.72% and 65.20% reduction in leakage power dissipation and improvement of 55.34% and 64.77% in delay is achieved for CNTFET RL-SRAM and RL-SRAM with body bias respectively in comparison of CNTFET SRAM cell. Results are also compared with previous work [1], which shows significant improvement in average power consumption, delay, and leakage power dissipation is achieved using CNTFET SRAM cell design without affecting the system performance. Stability of the memory cell is also examined by using butterfly curve and N-curve analysis.
... They are Bulk FinFET and SOI FinFET. The critical characteristic of the FinFET is that it has a conducting channel that is bounded by a thin silicon fin [10]. This mainly forms the body of the device. ...
ince last few years, the tiny size of MOSFET, that is less than tens of nanometers, created some operational problems such as increased gate-oxide leakage, amplified junction leakage, high sub-threshold conduction, and reduced output resistance. To overcome the above challenges, FinFET has the advantages of an increase in the operating speed, reduced power consumption, decreased static leakage current is used to realize the majority of the applications by replacing MOSFET. By considering the attractive features of the FinFET, an ALU is designed as an application. In the digital processor, the arithmetic and logical operations are executed using the Arithmetic logic unit (ALU). In this paper, power efficient 8-bit ALU is designed with Full adder (FA) and multiplexers composed of Gate diffusion input (GDI) which gained designer's choice for digital combinational circuit realization at minimum power consumption. The design is simulated using Cadence virtuoso with 20nm technology. Comparative performance analysis is carried out in contrast to the other standard circuits by taking the critical performance metrics such as delay, power, and power delay product (PDP), energy-delay product (EDP) metrics into consideration.
... To compare the performance of the SB-GNRFET-based FF versus conventional Si CMOS technology, different simulations are performed using a multigate Si CMOS predictive technology model (MG Si-CMOS PTM) [43] at the 7-, 10-, 14-, and 16-nm technology nodes, at nominal supply voltages of 0.7, 0.75, 0.8, and 0.85 V, respectively. The equivalent width of a MG Si-CMOS with n fins is defined by n × T fin + 2 × H fin , where H fin is the fin height of the transistor and T fin is the fin thickness [44]. The number of dimer lines, the number of ribbons, and the spacing between two adjacent ribbons are chosen such that the gate width of the SB-GNRFET becomes equal to the effective width of the MG Si-CMOS device. ...
Graphene nanoribbons (GNRs) are a good replacement material for silicon to overcome short-channel effects in nanoscale devices. However, with continuous technology scaling, the variability of device parameters also increases. Indeed, process, voltage, and temperature (PVT) variations affect the performance of GNR devices because of their small size. Moreover, the bandgap of GNRs is strongly affected by the number of carbon atoms across the channel width. This paper accurately evaluates the impact of such PVT variations on the performance of circuits based on Schottky barrier (SB)-type GNR field-effect transistors (SB-GNRFETs) in terms of their timing parameters, power, and energy–delay product (EDP). Extensive simulations and stability analysis are performed on both flip-flop and conventional six-transistor static random-access memory (6T SRAM) cells made using SB-GNRFETs under these variations. A statistical analysis of the impact of the PVT variations on the SB-GNRFET-based flip-flop is also performed using Monte Carlo simulations, considering the variation of one or all of the parameters, with or without line-edge roughness effects.
... Butterfly curve is used to estimate these noise margins. Butterfly curve for three operations can be obtained by plotting the voltage transfer curve for the inverter pairs and toggling the axes of one curve [34]. The square with a maximum length that can be embedded in the curve measures the noise margin. ...
Static Random-Access Memory cells with ultralow leakage and superior stability are the primary choice of embedded memories in contemporary smart devices. This paper presents a novel 8T SRAM cell with reduced leakage and improved stability. The proposed SRAM cell uses a stacking effect to reduce leakage and transmission gate as an access transistor to enhance stability. The performance of the proposed 8T SRAM cell with a stacked transistor has been analyzed based on the power consumption and static noise margin (RSNM, HSNM, and WSNM). The power consumption in the case of FinFET based 8T cell is found to be 572 pW at 22 nm technology node, which is reduced by a factor nearly as compared to that of CMOS based 8T cell. Further, in the case of FinFET based novel 8T SRAM cell at 22 nm technology node, the power consumption is found to be reduced by a factor of as compared to that of FinFET based conventional 6T SRAM cell. WSNM, HSNM, and RSNM of the 8T SRAM cell designed with FinFET logic are observed as 240 mV, 370 mV, and 120 mV respectively at 0.9 V supply voltage. When comparing with conventional 6T FinFET Cell, the proposed Cell shows 20%, 5.11%, and 7% improvement in WSNM, HSNM, and RSNM, respectively. The sensitivity of SNM with temperature variation is also analyzed and reported. Further, the results obtained confirm the robustness of the proposed SRAM cells as compared to several recent works.
... (M1&M2) and (M3&M4) form the cross-coupled inverter pairs (latches), and M5 and M6 are the access devices that allow the data stored in the cell to be accessed and modified by charging and discharging the output nodes Q and Q and bit lines BL and BL ���� during the read and write operations. The two access transistors play an extremely crucial role in determining the overall speed, power dissipation and stability of the cell [13][14][15]. Additionally, the three p-FETs, encircled in red in Fig. 1, are the bit line conditioning devices whose roles are to pre-charge and equalize the bit line voltages before each read and write operation. ...
There is an extremely high demand for a high speed, low power, low leakage, and low noise Static Random-Access Memory (SRAM) for high performance cache memories. The energy efficiency of SRAM is of paramount importance in both high performance and ultralow-power portable, battery operated electronic systems. In this article the factors affecting the over-all speed and total energy consumption of a conventional 6T SRAM cell/array with 6 FETs, particularly roles of access tran-sistors are analyzed to highlight the needs and directions for improvement. A hybrid 6T SRAM with two access FETs being replaced by light-effect transistors (LETs) and the electrical word lines replaced by optical waveguides (OWGs) is proposed. This hybrid SRAM is analyzed to reveal its potential in im-provement of the switching speed and thus total energy con-sumption over the conventional 6T SRAM. Numerical analyses of a prototype hybrid SRAM array of 64 KB show a factor of 7 and 34 reduction in read delay and read energy consumption, respectively; and 4 and 6 in write delay and write energy con-sumption, respectively, when the access FETs are replaced by LETs. The potential impacts on the peripheral and assist cir-cuits due to this hybrid structure and application of the LETs there are also briefly discussed.
... It demands compactness and longer battery life [1], [2]. The SRAM cell is used immensely and consumes large area in system-on-chip (SOC) devices [3] [4]. CMOS technology scaling is used to increase the performance and packing density of the devices [5]. ...
... Therefor this paper work is mainly focuses on the power consumption and stability on the DC current and also concentrated on delay due RC components. To overcomes these problems, IGFET with common multigate model is presented and finally it is tested in term of stability and functionality wise [8]. The SRAM cell design by using 7T with differential compose and single finished read activities working in the close edge district is proposed. ...
The presentation of the proposed FinFET based 6T SRAM cell has been assessed for its activity in low control space, indicating less SCEs, ultra little access time and high steadiness. The static clamor edge, spillage current, control dissemination and sub-limit current of FinFET based 6T SRAM cell at 32nm has been contrasted and MOSFET based 6T SRAM cell at 32nm innovation hub. It has been seen during the reproduction that the deferral among compose and read and power dissipation of FinFET based 6T SRAM cell is radically decreased when contrasted and regular MOSFET based 6T SRAM cell. The static power dissemination with differing width of Load, Driver and Access transistor of FinFET based model has additionally been weighed against MOSFET based model. At last, control dissemination and static clamor edge at 32nm for both MOSFET and FinFET based 6T SRAM cell have been contrasted all together with comprehend the subjectively conduct of the cell at various innovation hubs of the proposed FinFET model. It tends to be valued that the gadgets without anyone else's input don't add to the current joining period. Yet, until, a circuit investigation utilizing the proposed gadgets is attempted, the full advantages of joining can't be caught. Rationale and memory circuit plan in Nano scale system requires power over spillage flows with gadget level parameter varieties. After the wonderful decrease in Leakage current and power dissemination, a similar methodology is then executed to cutting edge SRAM cells. We have thought about different progressed proposed FinFET based SRAM cells with the customary progressed MOSFET based SRAM cells. The huge spillage decrease has been seen when we have changed from traditional MOSFET models to FinFET models. Finally, process parametric varieties at circuit level, gadget level and material level on FinFET based 6T SRAM cell is talked about and the instrument to control these varieties is introduced in the proposal. Procedure parametric varieties like word line, bit line, control supply tweaks is appeared and examined. Temperature impact is likewise appeared and talked about in the postulation. Every one of the recreations have been performed on Cadence Virtuoso at 45 nm innovation. Our investigation demonstrates that, utilization of FinFET gadget with characteristic body decreases spillage current and improves the driving capacity. Consequently, we presume that FinFET can develop as one of the promising possibility for decreasing spillage segments making it effective for low power and superior SRAM cell structure in nanoscale system. In this paper SRAM investigation as far as Static Noise Margin, Data Retention Voltage, Read Margin and Write Margin for low control application is considered. Static Noise Margin (SNM) is one the very pinnacle of fundamental limitations for structuring memory since it influences read edge just as the compose edge. In the SRAM cell SNM is identified with the NMOS and PMOS gadget's edge esteems. High Read and Write Noise Margin are additionally huge difficulties in the plan of SRAM.
... Concerning illustration for every those today's scenario, we have a few transistors actualized ahead a solitary chip which will be similarly little over the past outline execution. Likewise those measure is lessened the impact from claiming spillage current, spillage energy will be expanded in the out [1]. ...
At working to low control provision the primary estimation will be to decrease spillage parts What's more parameters. This stanza investigates a limitless join towards low spillage energy SRAM units utilizing new innovation organization and units. Those ram holds bi-stable cross coupled lock which need V_th higher to compose. Mode entry MOSFET What's more level V_th for peruse. Get mode MOSFET which is favored to low spillage present also control without at whatever twisting. In view of those perception of a CMOS five-transistor SRAM Mobile to high thickness and low force requisitions. This cell retains its information for spillage present furthermore certain input without invigorate cycle. This 5T SRAM Mobile utilization you quit offering on that one word-line What's more you quit offering on that one bit-line also additional read-line control. That new cell measure will be more modest over an routine. Six-transistor SRAM cell utilizing same outline tenets with no execution corruption, reenactment furthermore explanatory outcomes indicate purposed Mobile need right operation. Throughout read/write furthermore additionally the delay about new Mobile will be little over a six transistor SRAM cell. The new 5T SRAM cell holds lesquerella spillage current for admiration to those 6T SRAM memory cell utilizing rhythm 22 nm engineering organization.
