Fig 13 - uploaded by Supriyo Srimani
Content may be subject to copyright.
Similar publications
BACKGROUND
Caring for individuals with chronic conditions is labor intensive, requiring ongoing appointments, treatments, and support. The growing number of individuals with chronic conditions makes this support model unsustainably burdensome on health care systems globally. Mobile health technologies are increasingly being used throughout health c...
Citations
... The final result of the multiplication is got when the carry of the previous partial products are summed together with the next partial products [11][12][13][14]. This is as described as follows: ...
span>With an ever growing demand for low-power devices, it is a general trend to search for ways to reduce the power consumption of a system. Multipliers are an important requirement in applications linked to Digital Signal Processing, Communication Systems, Optical Computing, Nanotechnology, Low-Power Very Large Scale Integration and Quantum Computing. Conventional mathematics makes multiplication a very long and time consuming process. The use of Vedic mathematics has led to great reduction in the time required for such calculations. The excessive use of Urdhava Tiryakbhyam sutra in multiplication surely proves its effectiveness and simplicity in this domain. This sutra supports the process of pipelining, a method employed in reduction of the power used by a system. Reversible logic has been gaining demand due to its low-power capabilities and is currently being used in many computing applications. The paper proposes two multiplier systems: one design employs the Urdhava Tiryakbhyam sutra along with pipelining and the second uses reversible logic gates into the first design. These proposed systems provide very less delay for result computation and low hardware utilization when compared to non-pipelined Vedic multipliers.</span
... It save time in mathematical calculations, even when there were no computers [5]. DSP operations based on ancient Vedic Urdhava-Triyagbhayam [6], 8bits fixed point Vedic DSP processor [7] and 4*4 multiplier based Urdhva-Tiryakbhyam [8], and division using Vedic technique `Dhwajam' [9] are getting attention of researcher. In our paper we have designed a Vedic squarer using Vedic mathematical technique "EkadhikenaPurvena" meaning "one more than the previous". ...
EkadhikenaPurvena is a Sanskrit name which means "one more than the previous". This technique is used for squaring any big number but the condition is it should end with digit "5". Vedic mathematical formulas are used to solve tedious and cumbersome arithmetic operations. Tool is Xilinx ISE Design Suite 14.2 and Kintex-7. We have taken different frequencies and calculated its power. Today's demand forces us to design the low power energy efficient devices which takes lesser time for its execution. In our design there are 2 inputs and 1 output. The inputs are clocked and the number whose square we are supposed to calculate is 8 bits wide and the output is 14 bits wide (squared number). Many researchers have performed research on Vedic mathematics to solve DSP operations using Urdhava-Triyagbhayam multiplication sutra. We have done power analysis by varying frequency at different temperatures to make our Vedic squarer energy efficient. Temperatures taken in view are 56.7, 53.5, 40, 21 degree Celsius and Airflow is 250 LFM (Linear Feet Per Minute). Analysis results shows that the maximum power consumption is at 2.2 Billion Hertz and minimum power consumption is at 1400 Million Hertz. In respect to temperature maximum power is consumed at 56oC and minimum at 21°C.
... Many research work has been done using Urdhva-Tiryakbhyam e.g. DSP operations using Vedic Urdhava-Triyagbhayam multiplication formula [10], 4*4 multiplier using Urdhva-Tiryakbhyam [11]. A multiplier that takes 8-bit complex number as input, processes it and gives the result has been designed and used Vedic mathematics for high speed performance [8]. ...
We have taken different set of frequencies and done study of power by varying frequencies and with different SSTL Standard Used for Input/Outputs at fixed temperature i.e. 25 degree Celsius. SSTL family includes SSTL15, SSTL18_II, SSTL135, SSTL12, SSTL18_I. Power has been calculated on these standards and analysis has been done to find the standard with least power consumption and to make an energy efficient device. The proposed multiplication algorithm is coded in Verilog, synthesized and simulated using Xilinx ISE design suit 14.2.at the end we can conclude that there can be 34-50% power consumption reduced by using frequency scaling technique and using SSTL Standard used for Input/Output. The maximum power has been consumed by SSTL18_II and minimum power consumption is by SSTL12.
... Today's world demands implementation of techniques which take lesser time and is energy efficient so we have designed a Vedic divider. other researchers have also performed there research work in the field of Vedic mathematics like implementation of 4*4 multiplier using Urdhva-Tiryakbhyam in 45nm technology [8], another division architecture using another Vedic technique known as `Dhwajam' [9]. With the enrichment of new technology there is a huge demand of energy efficiency. ...
... A design of an 8 bits fixed point, asynchronous Vedic DSP processor core has also been studied [12]. Implementation of 4*4 multiplier using Urdhva-Tiryakbhyam in 45nm technology [13], another division architecture using different Vedic technique known as `Dhwajam' [14]. Vedic multiplier has been designed earlier using different Vedic formulas but this design using Nikhilam Navatashcaramam Dashatah vedic formula is completely a fresh work and is quite efficient [20][21].In this paper we have designed an energy efficient multiplier that consists of three inputs and one output. ...
In this paper we have designed an energy efficient multiplier using Nikhilam Navatashcaramam Dashatah Vedic technique. Vedic mathematics consists of 16 sutras and these sutras were used by our ancient scholars for doing there calculation faster, when there were no computers and calculators. Nikhilam Navatasaman is a Sanskrit word which menas “all from 9 and the last from 10”. In today’s work the demand is high speed, efficiency and should take lesser time. Appling these Vedic techniques reduces the system complexity, execution time, area, power and is stable and hence is efficient method. In this paper we have designed an energy efficient multiplier that consists of three inputs and one output. The temperature has been kept constant that is 25 degree Celsius. Airflow has been kept 250 LFM and medium Heat sink. IO Standards has been varied in order to achieve an energy efficient device. In this paper we have taken HSTL (High Speed Transceiver Logic) IOSTANDARD. In order to achieve speed and high performance in addition to energy efficiency, HSTL IO standard is used. HSTL family consists of HSTL _I, HSTL_II, HSTL_I_18 and HSTL_II_18, HSTL_I_12 and the analysis has been done on these IO standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA.
... A design of an 8 bits fixed point, asynchronous Vedic DSP processor core has also been studied [12]. Implementation of 4*4 multiplier using Urdhva-Tiryakbhyam in 45nm technology [13], another division architecture using different Vedic technique known as `Dhwajam' [14]. Vedic multiplier has been designed earlier using different Vedic formulas but this design using Nikhilam Navatashcaramam Dashatah vedic formula is completely a fresh work and is quite efficient [20][21].In this paper we have designed an energy efficient multiplier that consists of three inputs and one output. ...
In this paper we have designed an energy efficient multiplier using Nikhilam Navatashcaramam Dashatah Vedic technique. Vedic mathematics consists of 16 sutras and these sutras were used by our ancient scholars for doing there calculation faster, when there were no computers and calculators. Nikhilam Navatasaman is a Sanskrit word which menas “all from 9 and the last from 10”. In today’s work the demand is high speed, efficiency and should take lesser time. Appling these Vedic techniques reduces the system complexity, execution time, area, power and is stable and hence is efficient method. In this paper we have designed an energy efficient multiplier that consists of three inputs and one output. The temperature has been kept constant that is 25 degree Celsius. Airflow has been kept 250 LFM and medium Heat sink. IO Standards has been varied in order to achieve an energy efficient device. In this paper we have taken HSTL (High Speed Transceiver Logic) IOSTANDARD. In order to achieve speed and high performance in addition to energy efficiency, HSTL IO standard is used. HSTL family consists of HSTL _I, HSTL_II, HSTL_I_18 and HSTL_II_18, HSTL_I_12 and the analysis has been done on these IO standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA.
... High Speed Transceiver Logic also called HSTL, Stub Series Terminated Logic called SSTL and Transistor-Transistor Logic called TTL are few more IO Standards available on FPGA. Our Energy efficient Vedic multiplier [1][2][3][4][5][6][7][8] design is implemented on 40nm Virtex-6 and 28nm Virtex-7 FPGA. Vedic mathematics deals with a range of Vedic mathematical sutra and their applications to carry out tedious and cumbersome arithmetic operations [2]. ...
... Vedic mathematics deals with a range of Vedic mathematical sutra and their applications to carry out tedious and cumbersome arithmetic operations [2]. Other researchers have also performed their research work in the field of Vedic mathematics like implementation of 4*4 multiplier using Urdhva-Tiryakbhyam in 45nm technology [3], another division architecture using another Vedic technique ISSN: 2456-0065 DOI: 10.21058/gjet.2015.1202 known as 'Dhwajam' [4]. ...
In this project, an innovative design of energy efficient Vedic Multiplier using a prehistoric Vedic mathematics method known as “Anurupyena Shunyamanyat” have been implemented on FPGA. Anurupyena Shunyamanyat is a Sanskrit name which in simple words means ' proportionality 'or ' similarly '. This Sutra is highly useful to find products of two numbers when both of them are near the frequent bases like 10, 50, 500 etc (multiples of powers of 10). Lesser time and energy efficient is today’s world demand. Choice of IO Standard plays a very important role in power indulgence design. So, we have selected most energy efficient IO standard LVCMOS (Low Voltage Complementary Metal Oxide Semiconductor). Then, we try to achieve more energy efficiency with different technology (40nm and 28nm) based FPGA. Virtex-6 and Kintex-7 are the platforms which have been used in this project. In our paper we have implemented our code on Xilinx ISE Design Suite 14.2 were tested on 28nm and 40nm FPGA. In this project we have observed approx 87-88% decrease in leakage power dissipation when we shift from 40nm to 28nm technology based FPGA.
arithmetic operations, the processor consumes most of its time and hardware resources in performing multiplication when compared to other operations like addition and subtraction. The high resource- consuming and iterative in nature are Multipliers, which minimizes the operational efficiency of the processing unit. As a result of this designing, a multiplier to minimize the combinational path delay and to increase the efficiency will be a challenging factor. In ancient maths, Vedic mathematics has an exclusive method of mental calculation with the support of basic rules and standards based on sutras. In designing the Multiplier the utilization of Vedic mathematics yield an extreme significance in the performance of processors. An efficient multiplier section can increase the overall productivity of the processor. In this paper, a new design is proposed using Carry Select Adder based Vedic Multiplier module to minimize the path delay. The designs are simulated using Xilinx 8.1i and also it is implemented in Spartan 3E FPGA (Xc25100e) and in vertex 4 FPGA (xc4vfx12). The simulation results show that Carry Select Adder based Vedic multiplier module shows better results when compared to the other adders which are employed in Vedic multipliers.
This paper presents design of optimized high speed and low power Vedic multiplier based on Vedic sutra Urdhva Tiryagbhyam. Adiabatic logic is used to reduce the power consumption of Vedic multiplier and its performance is evaluated by comparing it with conventional MOS design. The power consumption of Adiabatic Vedic multiplier is less than power consumed by Vedic multiplier without adiabatic logic is analyzed. The circuit 2×2, 4×4 Vedic multipliers are designed and simulated on 180nm technology using Tanner EDA Tool 13.0.
