VDSL chip set functional block diagram 

Context in source publication

Context 1

... behavioral and logic synthesis, as replacement for conventional Verilog or VHDL design tools. Today there at least three active attempts to standardize on C++ class libraries for system design, even if with potentially not completely equivalent coverage in terms of semantic: SystemC [4], CynLib [5], SpecC [6]. Particularly, within the SystemC Initiative, IPsim (Intellectual Property Simulation) class library is an innovative high-level methodology to model software and hardware parts of digital electronic systems [7]. The main features of IPsim can be summarized as follows: a) Using an object oriented programming language such as C++ with no additional syntax. b) The modeling of a hardware block is made first at a high level of abstraction, without thinking about the real implementation, so that the simulation is faster. c) Then each IP or virtual component is refined at several levels of abstractions to meet all the particular specifications, following a typical top- down design flow. d) The IP-models can be reused to build new systems, i.e. they can become a part of the library. e) It allows delivering such models to possible customers or developers to be reused or to be considered as a “golden” model for a not existing system, or when the implementation details should be kept confidential. In this paper we present, as a case study, the IPsim modeling and simulation of a Very-high-bit-rate Digital Subscriber Line (VDSL) modem. After this Introduction, Section 2 describes the IPsim C++ modeling library. Section 3 briefly presents the case study of a VDSL modem while Section 4 deals with its IPsim modeling. In Section 5 a comparison between IPsim vs. VHDL is performed for a building block of the VDSL modem (a 2K complex FFT) and finally some conclusions are drawn in Section 6. IPsim is a C++ library providing most SoC modeling concepts. It has been developed as an object oriented extension on top of SystemC 2.0 as sketched in Fig. 2. The use of C++ models appears advantageous for describing and validating complex integrated system behavior, especially when internal block details are not available. IPsim is basically a library of C++ classes developed to build, simulate and debug the executable specification of a hardware system. It also includes important features for system design, such as flexible process scheduling and system performance based on latency and throughput characteristics. IPsim classes are used to implement the three main components typically found in every digital system: communication and synchronization (interfaces, channels, semaphores, etc...), behavior (FSMs, threads, etc...) and data storage (registers, RAMs, FIFOs, etc.) [7]. A list of IPsim main components is shown in Figure 2. The class Module, provided by the C++ library, is essentially a container of all IPsim objects. Note that each hardware block is described extending this C++ class. The behavioral classes define the functionality of an IP. This functionality can be just an un-timed algorithm or a more complex timed structure. Besides, the communication between blocks can be described at very high abstraction level (bus transaction level) as well as at a level very close to the implementation (cycle level). The refining of input/output communication protocols allows the designer to model at different level of abstraction the behavior and its interface trading off timing precision and simulation speed. For example, a complex IP can be modeled at the behavioral level internally and at the cycle level at the interface, allowing the validation of the IP within the other components of the system. This object- oriented approach makes it possible to isolate the behavior from the communication. The code used to write an IPsim model is mainly split into three parts: a) an include file for each IP block of the system used to declare the object with relevant threads and data structures; b) a source file for each IP block used to define the architecture and the functional part; c) a main file used to instantiate the blocks and the links between all the interfaces, to configure the entire system and to run the simulation (specification for blocks and channels clock signals and debug options are defined at this level). All these files are then compiled and linked, using any standard C++ compiler, with the IPsim library to obtain the executable model of the system. Then SystemC simulation outcomes the behavior of the executable IP model at every clock cycle. A waveform or a text file is generated to display input and output signal activity. Commercial SystemC simulators are now available from EDA vendors as an alternative to the community-source version available through the Open SystemC Initiative website [4]. IPsim has been used to obtain a high-level model of the Zipper/DMT Processor of a VDSL modem chip-set [8]. A digital processor based on the Zipper/Discrete Multi Tone (DMT) technique and an analog front end (AFE) circuit (see Fig. 4 for its functional block diagram) composes the VDSL chip set. The DMT modulation works with a frequency band ranging from 0 to 8.832MHz. This band is divided into 2048 sub-channels, the carrier of each channel can be modulated into constellation up to 2048- QAM (Quadrature Amplitude Modulation). The constellation size is calculated, for each carrier, by the bit- loading algorithm considering its signal to noise ratio. The complete solution is designed to operate at 50/60 Mbps compliant to ETSI and ANSI recommendations [9], [10]. Figure 5 shows the block diagram of the Zipper/DMT processor. It performs the data path functions of the Zipper-VDSL modem. The receiver pipeline receives signals issued from the ADC in the AFE and performs DMT demodulation. The resulting signals are passed to the De-mapper. The transmitter pipeline receives signals from the Mapper and performs DMT modulation. The resulting signals are sent to the DAC in the AFE. Transmission . The combination of the pre-processor and IFFT units enables the generation of 2N real samples from N (N= 2048) complex data inputs at 8.832 MHz. It also performs a circular permutation of a number of cyclic prefix (CP)/2 complex samples. The Pulse shaping unit performs bit-reverse to re-order the IFFT output. Additionally, it inserts the calculated prefix and suffix in the symbol and performs pulse shaping on extra samples to reduce frequency domain side lobes of DMT signals. The output signal is over-sampled, by a factor of 2, by the Interpolator (a half band filter). Finally, the clip noise shaper saturates the signal coming from the Interpolator to a Clip-level thereby quantizing the range for the DAC and modulates the generated clip noise into higher frequency (over 8.832 MHz). Two modes of clip-noise shaping (filtering) can be chosen for performance evaluation purposes: either a FIR filter with 10 coefficients or a simpler one composed of one delay filter. Reception . The Decimator sub-samples the signal, coming from the ADC, by a factor of 2. The Decimator is a half band FIR filter with 103 coefficients (26 no null 18 bit coefficients). The Decimator output is used by the automatic gain control (AGC) to adjust the analog power of the receiver by computing the DMT power signal in the digital domain. It delivers to the DAC, depending on the desired accuracy, a digital command on n bits (6, 8, 9 or 12) to control the analog programmable gain amplifier. The Windowing and FFT unit performs FFT on blocks of 2048 complex samples at 8.832 MHz frequency. Additionally, the FFT unit corrects the distortion introduced by windowing on the DMT signal. Finally, the Post-processing and Bit-reverse unit perform the bit- reversed re-ordering of the FFT output plus a computation of the actual complex samples at 8.832 MHz assuming that the FFT input is a stream of real data at 17.664 MHz. This post- processing assumes that the first samples are equal to zero. In this section the description of a simple IPsim block of the Zipper/DMT processor chain is provided in order to give an idea of this modeling approach. For a sake of clarity, we first detail two of the most important IPsim components for behavior and communications: Threads and Msgbox, respectively. Threads are activated each clock cycle when a specific condition is true. They are split in two sections, called enter and exit statements. The time between enter and exit statements is variable and it is given in terms of clock cycles ( delay ). At the end of the enter statements the task is suspended for a number of cycles equal to the defined delay minus one. In this way the Thread takes exactly the time defined by the delay . It is also possible to change the delay run time. Msgbox is used to connect an IPsim block to a communication channel, thus realizing high level inter- module communication; on the low-level of abstraction it improves signal-based communications of Verilog or VHDL. This class includes two important functions: send and receive . The former function is used by a Thread to check whether it can transmit through the Msgbox (no overwrite). If the Msgbox is not ready to send, then the Thread waits indefinitely until the Msgbox is ready and the Thread has the highest priority for dequeuing a message. The receive function is used by a Thread to check whether there is something to receive from the Msgbox. If the Msgbox has not received any data, then the Thread waits indefinitely until the Msgbox is ready and the Thread has the highest priority for dequeuing a message. Particularly, Figure 7 shows the IPsim model for the RX_windowing block (Windowing function in the RX data path of Fig. 5). Circles represent Threads (used for behavior), shadow rectangles represent RAM (used for data storage) and not-shadow rectangles represent Msgbox (used for communication). The dotted line represents the dependency between two Threads. When data are available in the Msgbox Port_receive , the Thread, named ...