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![Standard quaternary inverters presented in a [29] and b [10]](publication/331288711/figure/fig2/AS:960006249787423@1605894734903/Standard-quaternary-inverters-presented-in-a-29-and-b-10_Q320.jpg)
![Worst-case noise condition of the STI in [23] a without process...](publication/331288711/figure/fig4/AS:960006253993991@1605894735302/Worst-case-noise-condition-of-the-STI-in-23-a-without-process-variation-and-b-with_Q320.jpg)
![Worst-case noise condition of the STI in [7] (a) without process...](publication/331288711/figure/fig5/AS:960006253989890@1605894735544/Worst-case-noise-condition-of-the-STI-in-7-a-without-process-variation-and-b-with_Q320.jpg)
Multiple-valued logic (MVL) can lead to fewer interconnections inside and outside a chip. It can also increase computational performance. Despite these intrinsic advantages, MVL circuits are more prone to noise than the binary counterparts. Since the voltage range is divided into some narrow zones, it is essential to consider noise margins carefull...
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Nowadays, due to the high capabilities of nanotechnology in designing multi-valued logic (MVL) circuits, much research has been done to design MVL circuits in nanotechnology. The use of MVL circuits reduces chip interconnections, thereby decreasing the chip area and power consumption. Various methods have been proposed to produce logic ‘1’ in the t...
Citations
... STI circuits in [34] and [7] consume less power since two transistors are stacked, but the delay increases due to increase in transistors. The STIs are either working on single or dual power supply as tabulated in table 14. ...
... Four NMs, NM 0 , NM 1-, NM 1+ and NM 2 are calculated and the minimum of these four is considered as the noise margin. NM of proposed STI is 223mV, which is 69%, 32%, 30%, and 7% higher than [18], [34], [17], and [7] respectively 5.2. Comparison of TNAND gates TNAND gates are analysed and compared on numerous parameters in table 15. ...
Multiplication is a fundamental arithmetic process, although it necessitates more hardware resources. Researchers in advanced technology attempted to boost the speed and lower the power in digital signal processing applications by utilizing multipliers. The majority of digital signal processing applications demanded increased speed. In addition, ternary logic based on CNTFETs is a feasible alternative for Si-MOSFETs. The article proposes a ternary multiplier, which is designed using proposed ternary logical and combinational circuits that includes STI, TNAND, TNOR, and ternary decoder. The proposed and existing designs are simulated, compared, and analysed on the parameters of delay, average power, and noise using the HSPICE simulator. Therefore, the results show 10%, 81% and 81% improvement in delay, average power, and PDP respectively for proposed TMUL. The noise margin of the proposed TMUL is increased up to 54% over existing circuits. The proposed TDecoder, STI, TNAND, and TNOR are 95%, 97%, 81%, and 95% more energy efficient than existing designs, respectively.
... Multi-valued logic (MVL) designs are the solution to improve the interconnection computational complexity by increasing the logic levels. MVL designs also have the advantages of reduced chip area, improved capability and better data density [3]. Ternary logic is a subclass of MVL with radix 3 [4]. ...
... Therefore, it is crucial to analyse noise margins (NMs), especially for low-power circuit designs. NM is the circuit's capacity to withstand noise at input signal without causing the output to deviate from the permitted logic voltage level [3]. ...
Ternary logic offers faster response and low power consumption for digital systems, which minimizes the connection complexity, chip size and power consumption. Multi-threshold and geometry dependent properties of CNTFET make it a suitable alternative over the traditional Si-MOSFET for ternary logic circuit implementation. The proposed work minimizes the power dissipation, improves the speed and noise margin for designing efficient ternary circuits. In this article, one ternary decoder and two ternary comparators are designed and analysed. The proposed circuits are simulated and compared with existing circuits using HSPICE Synopsys tool. The proposed ternary decoder shows improvement up to 48% and 74% in power dissipation and power delay product, respectively, as compared to existing circuits. The proposed ternary comparator saves 82% power over other ternary comparators. Noise margin for proposed ternary decoder and ternary comparators is increased to up to 21% and 34%, respectively.
... Usually described in terms of voltage, this is a very significant characteristic with reference to circuit analysis [4]. Among the multiple-valued logic systems, binary systems have one of the most resilient noise margins [21]. To examine this characteristic, universal logic gates are simulated in the paper. ...
... Ternary logic shows itself as an efficient MVL because of its lower connection complexity, symmetric computing error, comparative greater noise margin, and a more simplified circuit design [20]. As previously discussed, the VTC curve is used to assist in illustrating and clarifying the concept of ternary noise margin [21]. ...
... In a quaternary logic system, four different logic levels are there which reduces the distance between distinct voltage levels and makes them more susceptible to noise than binary and ternary logic circuits. Formulae to calculate noise margin in an MVL circuit have been presented by (Takbiri et al., 2019). These formulae as shown below, have been used here to calculate noise margins of the proposed quaternary logic gates and presented in Table 3. ...
This paper presents novel power-efficient designs of quaternary logic gates like Quaternary Minimum (QMIN) and Quaternary Maximum (QMAX), Standard Quaternary Inverter (SQI), Standard Quaternary NAND (SQNAND), Standard Quaternary NOR (SQNOR) and Standard Quaternary XOR (SQXOR) using Carbon Nanotube Field Effect Transistor (CNTFET). The designs are based on Pass Transistor Logic (PTL) and use only three types of Carbon Nanotube (CNT) diameters 0.626nm, 1.018nm, and 2.27nm, which lead to lower fabrication costs and enhanced manufacturability when compared to the state-of-the-art designs. The designs are simulated in HSPICE with a 32nm CNTFET model provided by Stanford University, and the average power and maximum propagation delay obtained from the simulation results are compared with other existing designs. It shows that the proposed designs require 75% to 90% less power and they achieve 73% to 91% less Power Delay Product (PDP) than the latest designs.
... Ternary-based designs have been studied and researched as a promising alternative for designing efficient devices. Ternary designs are used in cloud server storage and big data because they can store more data in a single bit than binary designs [6]. ...
... The STI design [4] eliminates the transistors acting as resistors in [9] at the cost of dual voltage supplies ( . Similarly, the circuits in [5] and [6] demonstrate an improvement in energy when compared to the design [4], at the expense of greater transistor count due to the inclusion of PTI and NTI network in the same design. Although the STI design [7] has fewer transistors and a single voltage supply, the circuit [4] has higher noise margin. ...
... The output voltages , and in the equations above represent the voltage values 0, V DD /2, and V DD respectively. Additionally, the parameters are , and respectively when the curve shifts from 2 to 1 and from 1 to 0 [6]. ...
... in self-loaded circuits without significant routing and fan-outs capacitances, equalsized devices are used to reduce power dissipation [10], switching activity, and an appropriate noise margin [42]. Moreover, a small leakage current of the transistors [28] helps to achieve a smaller energy dissipation, so, the width of the transistors is considered with the minimum allowable size by technology, which here is 120 nm. ...
A new 1-bit digital comparator named 14T-SR-GDI is presented with gate-diffusion-input (GDI) and single-swing-restoration (SR) techniques to attain internal gates with high driving capability. The comparator has 14 transistors which produce full-swing outputs with low power consumption. In the 14T-SR-GDI, boosted inner signals are used to activate the output gates which result in a high-speed circuit with effective scalability and the enhanced driving capability for multi-bit structures. The comparator has a low power-delay-product (PDP) due to the small numbers of internal nodes and capacitances and efficient power-ground-free gates. The 14T-SR-GDI comparator, fully SR-GDI-based AND, and OR gates, construct a new tree structure for multi-bit magnitude comparators including 2-bit, 4-bit, 8-bit, and 16-bit comparators. The proposed 1-bit comparator is used in image processing for difference detection, and its efficiency is proved by image quality parameters. The post-layout simulations are performed for the 1-bit to 16-bit structures under TSMC 90 nm technology. The extracted results express a PDP with an average difference of 9.59% between the regular and post-layout modes. Also, the proposed 16-bit comparator is embedded in a pad with a total area of 4331.25 μm2. The designed magnitude comparators are key components in digital signal processors (DSPs).
... In ternary logic, there are three input logics {0, 1, 2} played a vital role those are having 0Vdd, 0.5Vdd and 1Vdd respectively. The voltage transfer characteristic of the ternary inverter is shown in Figure 11a which is appeared in unreliable manner [33]. For instance, the entire voltage value can be divided into three parts is illustrated in the Figure 11b. ...
... VTC curve of a ternary inverter[33] VTC curve of a STI, divided into three[33] VTC curve of a STI, divided into four[33] ...
... VTC curve of a ternary inverter[33] VTC curve of a STI, divided into three[33] VTC curve of a STI, divided into four[33] ...
Ternary adders have produced more benefits compared to the binary adders (i.e.) the ternary adder occupies less amount of area as well as produces less interconnect complexity. But the CMOS implementation of the ternary adders are failed to perform the process when the channel length is taken as 32nm. At 32nm technology, the CMOS transistors are exhibited undesired effects such as SCE, mobility degradation, etc., These issues are overcome by multi-gate devices. CNFETs (Carbon Nano-tube Field Effect Transistors) are the one of the technology to work efficiently when channel length is 32nm. In this paper, CNFETs based ternary prefix adders are designed. The power consumption is the most needed requirement for the VLSI system. So, this can be achieved by reducing the number of transistors. The reduction approach is called as the GDI (Gate Diffusion Input) logic is also included in the proposed prefix adder design. The proposed adder improved by reducing the power upto 83%, Energy upto 83%, current upto 78%, delay upto 96%. Finally, the PDP (Power Delay product) also reduced by 84% compared to existing ternary adders.
... In this case, one of the inputs is varied from 0 to V DD (here C in ) while the other two inputs are fixed as A = 0 and B = V DD . Here, different parameters such as V IL , V OL , V OH , V IH , NM L , NM H , NM are defined (described comprehensively in [44]). Also, the number of transistors for each circuit along with the related PDP are extracted and shown in Table 8. ...
A new 1‐bit full adder (FA) cell illustrating low‐power, high‐speed, and a small area is presented by a combination of transmission gate (TG), pass transistor logic (PTL), and float techniques. Using the proposed cell, a 4:2 compressor is implemented and its performance is investigated under diverse circumstances of voltage, temperature, and driving. The process and corners are evaluated through the process‐voltage‐temperature (PVT) variations and the Monte Carlo method (MCM), respectively. The accuracy and reliability of the proposed 4:2 compressor are confirmed carefully. Utilising the proposed FA and the compressor, an efficient 8‐bit subtractor is implemented for bioimage processing, in particular for difference detection of images. A new mechanism is presented to improve the detection performance of digital signal processors (DSPs) by the addition and subtraction of two images for their difference. The quality of the resulted image confirms the efficiency of the proposed circuits and the method. The high performance of the circuits makes them a promising candidate for the next generation of integrated circuits (ICs) applicable to medical image processing.
... Chiral vectors of transistors also have been optimized to use only zigzag carbon Nano-tubes (CNT) while SQI 32 used both zigzag and chiral CNTs. Besides as proved in Ref. 50 to increase the noise margin of the SQI gate as shown in Fig. 4 the voltage transfer characteristics (VTCs) needs to divide into six sections instead of four. Based on this, logics of "0" and "3" gain one and logics "1" and "2" gain two parts of the voltage band, which based on 0.9 V supply voltage are 0.3 V and 0.15 V, respectively. ...
By using CNFET technology in 32 nm node using a the proposed SQI gate, two split bit-lines QSRAM architectures have been suggested to address the issue of increasing demand for storage capacity in IoT/IoVT applications. Peripheral circuits such as a novel quaternary to binary decoder for QSRAM have been offered. Various simulations on temperature, supply voltage, and access frequency have been done to evaluate and ensure the performance of the proposed SQI gate, suggested cells, and quaternary to binary decoder. Moreover, 1000 Monte-Carlo analyses on the fabrication parameters have been done to classify read and write delay and standby power of proposed cells along with PDP of proposed quaternary to binary decoder. It is worth mentioning that the PDP of the proposed SQI gate, decoder, and average power consumption of suggested HF-QSRAM cell reached 0.92 aJ, 4.13 aJ, and 0.15 µW, respectively, which are approximately 80%, 91%, and 33% improvements in comparison with the best existing designs in the literature.
... Finally, none of the papers has suggested a methodical transistor sizing procedure. Similar to Fig. 1(a), the VTC curve of a ternary inverter must be divided into four equal parts from the x-axis (V in -axis) [36]. Several papers have incorrectly considered Fig. 1(b) as the ideal VTC curve for a Standard Ternary Inverter (STI). ...
Noise and variation are the two major challenges for the reliability of digital circuits, especially multiple-valued logic (MVL) circuits where the entire voltage range is divided into some narrow zones. In spite of few correct examples, many ternary inverters with reduced noise margins have been presented in the literature. The defect is mainly because of their improperly shaped voltage transfer characteristic (VTC). With proper transistor sizing, we can rectify the problem and provide uniformly wide noise margin values while maintaining power-delay product (PDP) low. As far as we know, none of the previous ternary inverters has been given based on a methodical transistor sizing procedure. In this paper, a systematic transistor sizing through physical equations is suggested for an existing standard ternary inverter (STI), whose original sizes for the carbon nanotube FETs (CNFETs) are inappropriate. This paper includes a comprehensive investigation to determine appropriate values for the physical parameters of the CNFET-based STI. Compared with the original design, with a negligible increase in circuit delay and area, simulation results show that the proposed ternary inverter can increase noise margin and static noise margin by up to 47.7% and 83.3%, respectively.
