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As the results of Moore's Law, Semiconductor industry has sophisticated the electronics by driving it down in deep sub-micron CMOS technology and has achieved low power consumption, less chip area and less fabrication cost. In 2015, with the claims of short term end of the Moore's Law, parallel research took place to enhance the efficiency of Syste...
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Traditional mixed-signal design verification is carried out separately by analog team who run transistor level simulation through different corners, and by digital team who run block simulation on RTL while using analog mixed-signal (AMS) behavior model to represent analog function. That method could not meet the verification requirements for advan...
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... mainly for prototyping and debugging purpose [10] . The RPi is equipped with open source modified ASR engine which is nothing but a set of files in a proper hierarchy (The Linus Torvalds Philosophy). ...
Speech recognition has always been an interesting subject of research since decades. With the change in time the tools, algorithms and the accuracy has drastically changed. Currently Speech processing is implemented based on application specific accuracy requirements and regardless of the implementation scheme the ultimate goal remains the same, to enhance speech processing engines up to an extent where natural language can be interpreted accurately in case of word or phoneme recognition and context prediction. Along with all of these needs when we apply speech processing to embedded systems we also need to be aware of the current research directions in it. On one hand the application development of embedded systems are now being massively focused on Internet of Things, the core researchers' concerns are still security and power efficiency. Here a state of the art scheme is proposed where speech processing is applied to the constrained IoT applications and the system has been made power efficient. For achieving so, this project covers two modules (nodes) of an IoT architecture where one is a major node while other is a constrained node and applies i-vector algorithm to increase PDF of the speech by means of speaker recognition through wake up call.
... When both UP and DN signal are high, they are fed to AND gate and it generates Logic 1 signal which is fed to the inverter which raises a RESET pulse. As soon as the RESET signal is fed to both D-FF, they approach to their initial states i.e. state 0. RESET signal delay can affect switching activity of transistor thus more inverter delay stages are added after AND gate which can minimize RESET pulse delay and help D-FFs to get back on its initial states as soon as possible [16]. ...
With the prevalence of VLSI technology and electronics devices becoming smaller, denser, smarter and long lasting, the research in the field of low voltage applicability and low power consumption is turning omnidirectional among which one direction leads towards the depth of faster and precise clock generation which is achieved on the foundation of PLL. The time has come to break one of the famous Silicon Valley golden rules which states " Higher the clock frequency, Greater the power consumption ". Keeping the trivial relationship between power consumption and power dissipation in mind, lowering supply voltages is the most effective method to reduce power consumption. At lower supply voltage, it is challenging to optimize each block of PLL for Low Voltage operations. A Low voltage High Frequency ALF Charge Pump PLL is proposed. It employs a differential Charge pump with an active loop filter to compensate current mismatch and reduces reference spurs. A Voltage Controlled Oscillator is designed with body bias technique providing wide capture range and low power consumption. A D Flip Flop PFD is designed with TSPC dynamic logic to achieve zero or minimum dead zone and is able to detect large phase and frequency difference.
... Also phase noise performance of PLL depends on quality factor of inductor and it is difficult to achieve required quality factor in digital CMOS technology. As Spiral inductor in LC-VCO occupies a large amount of chip area which reduces advances to be achieved by scaling [6]. At low supply voltages large threshold voltages of transistors may cause CMOS switching to slow down which can prevent VCO and frequency divider to operate on high frequencies. ...
A Low voltage Power Efficient Phase Locked Loop is designedforSoCs. A MCSS Charge Pump is introduced to reduce leakage current and current mismatch. In order to achieve wide tuning range at low VCO gain Kvco. A Low voltage VCO (LV-VCO) for low voltage application is designed by a Ring Oscillator using 4-stage differential delay cells with low voltage segmented current mirror (LV-SCM) for biasing purpose. Proposed PLL is implemented in 90nm CMOS Technology and measures phase noise and power consumption for enhanced CP and RO-VCO.
