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11 Typical FPGAs Data flow  

11 Typical FPGAs Data flow  

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Figure 2.12 FPGA design flow [16]  
Figure 2.18 DSPE48 slice diagram [19]  
Figure 2.15 Virtex 5 CLB block diagram [18]  
Figure 2.3 Interrogation areas method  
+5 Figure 2.17 Carry chain logic diagram [18]  
Implementing a Highly Parameterized Digital PIV System On Reconfigurable Hardware
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This paper presents PARPIV the design and prototyping of a highly parameterized digital Particle Image Velocimetry (PIV) system implemented on reconfigurable hardware. Despite many improvements to PIV methods over the last twenty years, PIV post-processing remains a computationally intensive task. It becomes a serious bottleneck as camera acquisiti...
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