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Typical DICE schematic drawn so that the halves are interleaved, not separated

Typical DICE schematic drawn so that the halves are interleaved, not separated

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Techniques are described for minimizing the number of cells in a digital logic library, scaling and porting the cells to process nodes that do not nominally support scaling, and increasing the separation of critical node pairs without unduly disrupting the design process. A new compact modular 8T self-voting latch reduces circuitry by over half, al...

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... the bonding structure can be obtained from the vendor, but increasingly pads are treated as IP). While the DICE was originally designed as a "dual interlocked" circuit, there is a long running trend to minimize its area by drawing both halves as one circuit, as in Figure 4. This is counter-productive at nanoscale as it brings the critical node pairs too close together, and in fact the point of Menuoni's investigation is that: "... the tolerance to SEU is affected by the charge sharing between sensitive nodes for DICE latches designed with highly scaled processes. ...

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