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Accurately extracting weak signals is extremely important for overall performance and application in optoelectronic imaging and optical communication systems. While weak signals are susceptible to noise, adaptive filtering is a commonly used noise removal method. Still, its convergence speed is slow, the steady-state error is large, and the anti-in...
Detection of targets with small Doppler frequencies of linear-frequency modulated continuous wave radars is the main task of this article. The moving target indicator (MTI) is used to reject the fixed targets and high-speed targets through the radar research area. In this work, targets with small Doppler frequencies can be detected perfectly based...
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... On average, a CSD representation contains approximately 33% fewer non-zero bits than its binary counterpart. This in turn implies hardware savings of about 33% per coefficient [8,10]. ...
This paper presents the implementation of Artificial Neural Network (ANN) architectures on FPGA for image compression and decompression. ANN's are used in wide range of applications in different domains because of their advantages over conventional computation. The key functional components of artificial neuron are adders and multipliers. The main constraint in the implementation of neural network on FPGA is the area occupied by the multipliers. In this paper artificial neural network architecture is implemented using Canonical Signed Digits (CSD) based multipliers, Use of CSD multipliers in implementation of neural network can give area advantage. Two ANN architectures 4:4:2:2:4 and 16:16:8:8:16 have been studied for 50% image compres-sion. Intensive MATLAB simulations were carried out and the best performing weights and biases are selected. The neural network is implemented on Virtex-IIpro FPGA. The hardware functionality was verified using Xilinx Chipscope Pro Analyzer 10.1 tool.
... Such advantages include flexibility and programmability, but most of all, availability of tens to hundreds of hardware multipliers available on a chip [3]. The LMS adaptive filter enjoys a number of advantages over other adaptive algorithms, such as robust behavior when implemented in finite-precision hardware, well understood convergence behavior and computational simplicity for most situations as compared to least square methods [4]. Identifying an unknown system has been a central issue in various application areas such as control, channel equalization, echo cancellation in communication networks and teleconferencing etc. Identification is the procedure of specifying the unknown model in terms of the available experimental evidence, that is, a set of measurements of the input output desired response signals and an appropriately error that is optimized with respect to unknown model parameters. ...
... The key feature of the LMS algorithm is its simplicity. It requires neither measurement of the correlation function, nor matrix inversion [4] .It uses Mean Square Error (MSE) as a criterion. LMS uses a stepsize parameter, input signal and the difference of desired signal and filter output signal to frequently calculate the update of the filter coefficients set [3]. ...
Adaptive filters, as part of digital signal systems, have been widely used, as well as in applications such as adaptive noise cancellation, adaptive beam forming, channel equalization, and system identification. However, its implementation takes a great deal and becomes a very important field in digital system world. When FPGA (Field Programmable Logic Array) grows in area and provides a lot of facilities to the designers, it becomes an important competitor in the signal processing market. In general FIR structure has been used more successfully than IIR structure in adaptive filters. However, when the adaptive FIR filter was made this required appropriate algorithm to update the filter’s coefficients. The algorithm used to update the filter coefficient is the Least Mean Square (LMS) algorithm which is known for its simplification, low computational complexity, and better performance in different running environments. When compared to other algorithms used for implementing adaptive filters the LMS algorithm is seen to perform very well in terms of the number of iterations required for convergence. This phenomenon can be achieved by a sufficient choice of bit length to represent the filter’s coefficients. This paper presents a lowcost and high performance programmable digital finite impulse response (FIR) filter. It follows the adaptive algorithm used for the development of the system. The architecture employs the computation sharing algorithm to reduce the computation complexity.
... The latter product serves as the output of the cell, and the weighted sum that constitutes the FIR filter output is generated by adding the outputs of all of the cells [6].The digital filtering process can be described, in a very simplified manner, as the result of a convolution between the input (sampled) signal and the coefficients (also called "parameters", or "tap") of digital filter [7].Before a filter can be designed, a set of filter specifications must be defined, suppose that we would like to design a low-pass filter with a cutoff frequency .The frequency response of an ideal low-pass filter with linear phase and a cutoff frequency , is ...
... The low pass FIR filters design with sampling frequency =1000Hz,cutoff frequency =100Hz,and normalized frequency=0.2, based on Kaiser window design method with four values of beta (0. 5,3,6,9),and three values of specify order (20th, 70th, 200th).These filters used to remove the high frequency noise from ECG signal. ...
... The design of low pass FIR filters based on adjustable window design method implementing by using FDA tool and win tool from mat lab (R2010a) programs. Tables (2,3,4,5) show the simulation results of study the effect of four values of beta (0. 5,3,6,9),and three values of specify order (20th, 70th, 200th) on the FIR filters performance, where: Leakage factor = ratio of power in the sidelobes to the total window power,but the relative sidelobe attenuation = difference in height from the mainlobe peak to the highest sidelobe peak, and mainlobe width (-3dB) = width of the mainlobe at 3 dB below the mainlobe peak. (12,13,14) show the effect of four values of parameter β=0.5,3,6,9 respectively on the performance of low pass FIR filters when the filter order in fixed value, in time domain and frequency domain. ...
The main contribution of this paper is to design a digital finite impulse response filter using the particle swarm optimization (PSO) algorithm combined canonical signed digit (CSD) representation. The design has been done based on matching certain frequency response and the filter coefficients in CSD representation with limited bits and some of coefficients to be zero, simultaneously. Using CSD representation, multipliers can substitute adders, shifters and subtractors. In filter design, the results show that combining PSO and CSD representations simultaneously is better than combining PSO and CSD sequentially. In addition the results, if the common adders and subtractors were computed for all filter coefficients that specified in CSD representation, significantly reduce the complexity of the hardware implementation of digital FIR filter.
Design of a 96-times interpolation filter applied in audio signals processing in the system which adopts the cascaded half-band filters and CIC filter. The design is simulated with the MATLAB tool and generated by the Verilog HDL. At last shows the comparison of the RTL circuits and the simulation.
Low power reconfigurable architectural approach for finite impulse response(FIR) filter is proposed. This is suited for fixed filter order. To obtain reconfigurability in low power fir filter architecture variable input word length, different coefficient word length, reduced signal representation is used. In existing methods, low power is achieved by minimizing number of adders and multipliers. In the proposed method by considering the filter coefficient and inputs, filter dynamically changes the filter order to achieve dynamic power savings with minor degradation in performance. When the multiplication of input data and filter coefficient is so small the multiplication operation is cancelled and the multiplier is turned off to reduce the power consumption.
