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The operation of analog circuits from ultra low supply voltages becomes necessary due to semiconductor technology scaling. Yet traditional design techniques cannot be used. In this paper, we review techniques that allow analog circuits to operate with supply voltages as low as 0.5 V. Biasing considerations are given, and robust bias circuits are di...
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Context 1
... complete OTA can be composed of two stages such as the one described above, as shown in Fig. 4. The input stage's output common-mode bias of 0.4 V guarantees that the input devices of the second stage are correctly biased. The output common-mode voltage of the second stage is set to 0.25 V by decreasing the DC drop across R 2A and R 2B to 0.15 V. Similarly to what is done in the input stage, an negative resistance implemented by ...
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... OTA in Fig. 4 requires an accurate level shift volt- age to bias the pMOS load transistors compared to the out- put common-mode level. This level shift is set with the bias current I ls through a resistor (see Fig. 4). A current source is designed using a single nMOS device. To increase the in- version level of this device, its bias voltage is ...
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... OTA in Fig. 4 requires an accurate level shift volt- age to bias the pMOS load transistors compared to the out- put common-mode level. This level shift is set with the bias current I ls through a resistor (see Fig. 4). A current source is designed using a single nMOS device. To increase the in- version level of this device, its bias voltage is applied both through the gate and the body. A replica of this current source is used in the biasing circuit as shown in Fig. 5. An error amplifier servos the current in the current source so that a voltage ...
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... is applied both through the gate and the body. A replica of this current source is used in the biasing circuit as shown in Fig. 5. An error amplifier servos the current in the current source so that a voltage drop of V DD /2 is established across a replica resistor. The voltage developed by this circuit, V ls , is con- nected to M7 and M12 in Fig. 4, as shown there. By ap- propriate sizing the resistors and current sources in the am- plifiers the desired level-shifting voltage drops can now be generated in the ...
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... now discuss the generation of the bias voltage V bn in Fig. 4, which adjusts the biasing level of the nMOS input devices in relation to the pMOS load devices and allows to control the output common-mode voltage of the OTA. The biasing loop is shown in Fig. 7. This loop adjusts the V bn of a replica of one amplifier stage with an input common-mode voltage of 0.4 V so that its the DC output ...
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In this paper we present an ultra low-voltage bidirectional and continuous time current mirror based on clocked semi-floating-gate
transistors. The current mirror may be used with supply voltages down to 250mV and frequencies up to several hundred MHz.
The simulated data presented are obtained using the Spectre simulator provided by Cadence and valid for a 90nm TSMC CMOS process.
KeywordsFloating-gate–Current mirror and CMOS–Low-voltage–Analog floating-gate circuits–Current mode
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