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While one-bit ΣΔ modulators are widely used in Analog to Digital conversion stages due to their inherent linearity and precision, it is less common for the entire digital processing path to operate in single bit mode at the oversampled rate of the conversion system. The conventional approach has been to decimate the signal bit stream after conversi...
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... small fragment of the adder tree is shown in Fig. 6 coefficient pairs, so that the adder tree comprises 11 levels, the first few adder stages will have inputs in the range of 2 to 8 bits, which can easily be mapped to a single LUT in a typical FPGA architecture while the remainder will com- prise small ripple-carry blocks from three to 12 bits long. Note that it would be equally ...
Citations
... Various SDM-based DSP applications for word length reduction and hence reducing the overall system complexity are reflected in the literature that includes but is not limited to simple arithmetic units [9][10][11], FIR filters (fully or partially transformed to single-bit) [12][13][14][15][16][17][18][19], IIR filters [20][21][22], and some complex adaptive filter structures [23][24][25][26]. ...
Image processing has widespread uses practically in every branch of science and arts. Processing images is more difficult than processing sound or data as there are more bits in the high pixel quality image. It requires more space to store the image, more bandwidth to transmit it, and more time and resources to process. An image's complexity may decrease if its bit size is decreased. Sigma-delta modulation, or SDM for short, is an alternative method of minimizing data-word length to compression. Digital signal processing (DSP) systems can be made simpler by using the SDM approach, which was first created for analog to digital conversion (ADC). This paper suggests a novel way to use SDM in MATLAB for improved image processing. Consequently, the suggested single-bit SDM-based image arithmetic architecture is tested and compared with the traditional image arithmetic techniques. Additionally, to see the noisy channel influence on the traditional and proposed systems, some statistical metrics are also studied at different noise variance values, such as signal to noise ratio (SNR), mean square error (MSE), and Peak SNR value. The suggested architecture for the SDM-based image arithmetic precisely matches the addition and subtraction results of the conventional design, even yielding a higher SNR and the same Peak SNR as the traditional methods. In contrast, the outcomes of division and multiplication fall within an acceptable range. For better results the over-sampling ratio (OSR), an inherent characteristic of SDM must be increased at the cost of more processing cycles. Therefore, the trade-off between fewer resources, limited transmission bandwidth, and comparatively more cycles is provided by the SDM-based technique.
... In the domain of optimized implementation of DSP systems, the authors have proposed various new algorithms of multipliers [10,11,[15][16][17], FIR filters [5][6][7][8][9], matched filters [2], and adaptive channel equalizers [13]. ...
Several works report on overcoming the challenge of complex general-purpose signal processing algorithms that result in quick utilization of chip area resources (like FPGA in implementing system on chip or network on chip). However, with the advent of machine learning and deep learning algorithms, reducing this complexity and immense use of resources is a challenging task that can improve the system’s performance in real time. One of the approaches is algorithm optimization, which consumes fewer resources and produces an equivalent performance. This approach may likely be accepted in less-sensitive applications, like voice or video processing. Recently, an optimized algorithm of correlation-less Wiener–Hopf-based adaptive channel equalizer is reported, in which the overall complexity of the system is reduced by employing a more compact way of weight optimization. This paper is the continuation of that work that reports the modification in the Steepest-Descent-based adaptive channel equalizer algorithm by keeping the autocorrelation matrix out of the algorithm. The proposed design is simulated and tested at equivalent spectral performance and produces comparable performance with fewer chip resources when translated on FPGA. The proposed design supports that algorithm-level optimization may be accepted extensively for the optimal hardware-based design of DSP systems.
... Originally developed as an analog-to-digital conversion methodology aimed at audio and biomedical applications [6,7], SDM has more recently been used to reduce the processing complexity in numerous general-purpose, single-bit digital signal processing algorithms. This has included simple arithmetic units [8][9][10], FIR filters (fully or partially transformed to single bit) [11][12][13][14][15][16][17][18], IIR filters [19][20][21], and some complex adaptive filter structures [22][23][24][25]. Other recent examples of SDM-based short word length systems include adaptive channel equalizers using a µ-less approach [26], Weiner filters [27], Matched filters [28], digital arithmetic units [29], and smart sensor communications [30]. ...
... The Weiner filter is one of more straight-forward and well-known methods of adaptive channel equalization [16]. It is a linear filter that computes a statistical estimate of an input signal by filtering a known, related signal and using that to produce an estimate of the unknown input. ...
Filtering, transformations, and convolution in digital signal processing (DSP) are relatively resource-intensive algorithms, typically involving massive computations and complex processing architectures. Effective methods to manage this complexity include reducing the data word length using techniques such as sigma-delta modulation (SDM) and algorithmic optimization, either targeting coding style or via changes to the algorithm itself. In this paper, an SDM-based autocorrelation-less Weiner filter is proposed and compared with traditional multi-bit and SDM-based single-bit Weiner filters. The proposed design is first functionally verified using MATLAB simulations , and statistical parameters such as Signal to Noise Ratio (SNR), Mean Square Error (MSE), and Probability of Error (PE) are derived. The results show that the proposed design offers comparable performance to conventional filters. The proposed autocorrelation-less filter and equivalent conventional filters are then synthesized in FPGA for area-performance analysis. The SDM-based autocorrelation-less Weiner filter demonstrates a 30% improvement in performance over an equivalent traditional filter, which in result provides the shift in operating frequency from approximately 240 MHz to around 340 MHz, with about 63% less resources consumption. This improved performance and reduced resources increase the potential range of applications for this Weiner filter.
... Some work proposes similar techniques for control applications [5,30]. Comparisons of multi-bit and SDM techniques in FPGAs and ASICs are proposed in [17,20]. SDM is used in direct stream digital (DSD) audio [21], and there are recent proposals to implement linear filters directly in this format [25]. ...
Most digital active noise controllers have an intrinsic delay due to reconstruction and anti-aliasing filters. These delays may make them less attractive when compared with analog implementations. This delay is critical for broadband active noise control performance, even though the same is not valid in the narrowband case. The delay can be reduced by using custom design filters for the application with large transition bands but cannot be made close to zero. Also, the sampling rate can be increased, but this causes a significant increase in the computational cost since the number of control filter output calculations per second increases and the size of the control filter increases. This work proposes a way to reduce these delays almost to zero without a substantial increase in the computational cost by using the quantization and noise shaping techniques used in sigma-delta analog-to-digital (AD) and digital-to-analog (DA) converters. Sigma-delta AD and DA converters are used but without the typical filter. The controller filter impulse response is also oversampled, and the resulting filter is implemented at a high frequency but using just a few bits, resulting in low computational complexity. The AD downsampling filter and the DA reconstruction are not needed because noise shaping moves the quantization error to high frequencies that are not audible and that are filtered naturally by the acoustic transducers. However, standard adaptive filtering algorithms working at a low sampling frequency are still used to choose the control filter.
... This work is further investigated by [34] that proposes a new FIR-like filter design using sigma-delta modulation. In [17], authors have synthesized the proposed [34] FIR-like filter on FPGA and compared ternary FIR-like filter in single-bit (SBTFF) with FIR filters in multi-bit on its equivalent spectral performance with several orders of the filter and varying oversampling ratio (OSR). The SBTFF filter coefficients and their input were in ternary format (i.e., 1/0/+ 1). ...
In the recent past, a new set of digital signal processing algorithms are developed called short word length (SWL) DSP systems to mitigate the multiplier complexity that is an inherent part in most DSP functions. In SWL algorithms, the critical element is sigma-delta modulation (SDM). In this paper, we present the design, implementation, and hardware synthesis of the FIR filter and adaptive algorithms with the conventional and proposed multiplier schemes. Two proposed short word length adaptive algorithms namely Wiener and Steepest-Descent are compared with their counterpart LMS algorithm using conventional and proposed multiplier schemes. The hardware synthesize of these algorithms is done using Xilinx Spartan-6 and Vertex-7 FPGA and comparison is done based on area-performance-power. The overall results show that the sigma-delta modulation based adaptive DSP algorithm outperforms and is an efficient approach for mobile communication.
... VLSI is good for rapid prototyping and fast implementation of complex DSP functions at one side; on the other hand, it is a challenging task to bring out those complex DSP systems into compact form along with optimal performance and minimal power usage, especially battery dependent portable devices like mobile phones. The researchers around the world have accepted that challenge and are working to give the preeminent solutions [1][2][3][4] to fulfill huge competing requirements [5]. ...
This paper compares LMS filter-based adaptive channel equalizer, implemented on Vertex 7 FPGA using several existing and proposed multipliers. The three main performance parameters taken into consideration are the consumed resources (in terms of lookup tables), utilized power (among various design components), and the performance achieved (in terms of observed frequency). The results show the area-power-performance tradeoff amongst the conventional and proposed multipliers based designs. It is to mention that the proposed multipliers result in more compact systems due to less utilization of resources in all means.
... Its more applications are found in digital filter design [1][2][3][4][5], and a few in the domain of adaptive signal processing using least mean square (LMS) algorithm and its variants [6][7][8][9]. The conventional LMS family of adaptive algorithms fail to converge if the filter response is represented in single-bit format. ...
Recenlty, short word length DSP systems are proposed and reported that they outperform compared to their counterpart multi-bit systems in the sense of area-performance-power analysis. In this continuation, this paper presents the application of sigma-delta modulation (SDM) in the design of adaptive channel equalizer using the Wiener filter for wireless and underwater acoustic communication (UWA). To validate the application, various aspects of design are taken into consideration and comparison is carried out with contemporary (i.e., multi-bit) approach. Besides, FPGA based implementation of SDM based design and conventional approach is also carried out to endorse the proposed algorithm to be used in hardware based implementation. The results given in terms of area -perfromance analysis show that proposed algorithm works as desired and it opens the way of using the sigma-delta modulation in adaptive signal processing domain for UWA that has remained a quite challenging task ever before.
... In [2,3], mathematical model of low pas filter has been developed to guess the required performance results in stop band attenuation at worst. Furthermore, well-organized filtering of innovative bit-stream configuration is anticipated in [4]*, and Exploration of ternary FIR-filter at diverse oversampling-ratio and acquired the result in MATLAB that indicated the influence on the structure and enactment of stable ternary-FIR filter in terms of stop-band attenuation and also estimate the area performance-tradeoff at diverse oversampling-ratio thru created were stated in [5] and in [6] which revealed the contrast of sigma-delta modulation founded short word length & multi bit techniques. In this paper we considered the sigma-delta modulation-based ternary bandpass-like digital filter via FFT interpolation techniques at diverse oversampling-ratio and compared the result to multi-bit bandpass digital filter in terms of stop band-attenuation. ...
Recently, various general-purpose sigma-delta modulation based general purpose DSP algorithms have been reported that possess simpler multiplier complexity, lower power consumption and less chip area features. Here in exploration, our goal is to carry on designing a ternary-bit DSP algorithm in which significant design element is a sigma delta modulator. The formation sigma-delta (SDM) has an amount of very pleasant and attractive possessions and inborn linearity which is extensively consumed in communication systems. Signal is sampled more than that of Nyquist rate commonly word used oversampling and classically have a very short word length (i-e one-bit, binary or ternary) in sigma delta modulation technique. In this paper the design and simulation of ternary Band pass digital filter using sigma-delta modulation done in Mat-lab at different over-sampling ratio and compare it to multi-bit Band pass digital filter.
... Examining many different solutions, the single-bit systems with ternary coefficients are said to have simpler hardware for digital filters. Also, they are said to provide better dynamic range flexibility as compared to the binary filtering [2][3][4][5][6]. ...
... 1}. It is explained in literature that a ternary filter displays higher signal-to-quantization-noise ratio (SQNR) compared to conventional designs [5]. SQNR determines the ratio of the signal strength to the strength of the quantization noise introduced if there are errors in representing continuous signal samples during quantization.This design of single-bit ternary matched filter comprises of two parts: the ternary coefficient generation followed by designing of Matched filter using these coefficients in MATLAB. ...
... The structure of RDM is shown in Fig. 3. The z-domain transfer function of the second order RDM is [5]: ...
Matched filtering has found its way in many diverse applications such as communication, signal processing and more. The emphasis of this paper is on the design and analysis of a sigma-delta (ΣΔ) modulated ternary Matched Filter aimed at digital signal processing. The filter coefficients are made ternary {+ 1, − 1, 0} using the Ternary Quantizer. The performance of the new design is measured on the basis of Probability of error versus Signal-to-noise ratio and it was discovered that the performance curve of the single-bit designed Matched Filter is approximately in agreement with the theoretical SNR versus Probability of error curve and works satisfactorily satisfactorily like a multi-bit Matched Filter and as an extension, the functionality of the above mentioned design is also generated on Xilinx System Generator and is successfully synthesized, simulated and verified on FPGA.
... Designing FIR low pass filter using traditional methods require more coefficients if sharp cutoff or no phase distortion is required and actual response (Ω) is not more approximating to desired frequency response (Ω) within a given specification in magnitude and phase [11], [12]. In recent past, one of the alternatives to this approach reported is short word length DSP systems [13], [14] in which sigma-delta modulation is a key element. However, in this research paper we have attempted to present the PSO based FIR filter designed in MATLAB; output of PSO is set of optimized coefficients whose response is approximating to the ideal response. ...
Digital filters are the most significant part of signal processing that are used in enormous applications such as speech recognition, acoustic, adaptive equalization, and noise and interference reduction. It would be of great benefit to implement adaptive FIR filter because of self-optimization property, linearity and frequency stability. Designing FIR filter involves multi-modal optimization problems whereas conservative gradient optimization technique is not useful to design the filter. Hence, Particle Swarm Optimization (PSO) algorithm is more flexible and optimization technique based on population of particles in search space and alternative approach for linear phase FIR filter design. PSO improves the solution characteristic by giving a novel method for updating swarm's position and velocity vector. Set of optimized filter coefficients will be generated by PSO algorithm. In this paper, PSO based FIR Low pass filter is efficiently designed in MATLAB and further Xilinx System Generator tool is used to efficiently design, synthesize and implement FIR filter in FPGA using SPARTEN 3E kit. For an example specifications, output of PSO algorithm is obtained that is set of optimized coefficients whose response is approximating to the ideal response. Hence, functional verification of the proposed algorithm has been performed and the error between obtained filter and ideal filter is minimized successfully. This work demonstrates the effectiveness of the PSO algorithms in parallel processing environment as compared to the Remez Exchange algorithm.
