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4-bit ripple carry adders (RCA), 12-bit carry select adders (CSA), and a 4times4 Braun multiplier, based on lowest-number-of-transistor full adders, were designed and simulated. The designed full adders consist of 10 transistors and were used for n-bit adders with output voltage levels having a maximum of one threshold voltage (Vr) degradation. The...
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... of digital Integrated Circuits for many applications relies on three major criteria: Low power consumption, reduced chip area, and high speed. Using lower number of transistors to implement a logic function is beneficial in reducing the device and interconnect parasitic and reducing the chip area, resulting in lower time delay and potentially lower power consumption. However; the problem of threshold- voltage (V T ) loss of the output voltage levels, of those low- number-transistor circuits [2], may lead to faulty operation and higher leakage currents, especially for 0.18μm and subsequent CMOS technologies. Reducing the number of transistors of 1-bit adder design, for lower power consumption and higher speed in 0.35μm and older CMOS technologies was investigated [1-4]. However, many low-number-transistor adders do not operate correctly at low supply voltage in 0.18μm and subsequent CMOS technologies due to V T loss problem. The goal of this work is to design the lowest–number-of-transistors that can be used successfully in an n-bit adder or n-bit array multiplier. The targeted technology is 0.18μm CMOS Technology. This paper presents two 10-Transistor (10-T) and one 12-T Adder designs for n-bit adders and multiplier respectively. The two 10-T designs were not analyzed or studied before even though they were two of the forty-one 10-T adders mentioned in [2]. Adding one series-connected (stack) transistor to the circuit does reduce the power dissipation. The design of 12-T adders is reported here for the first time targeting their use in n- bit Multipliers. The two 10-T adders suffer from one V T loss instead of two V T as in many other designs [1], [3], [4]. The 12-T adder design has only one output (Sum) suffering from one V T loss while C OUT has full voltage swing. A 4-bit RCA, a 12-bit CSA adder, and a 4-bit Braun multiplier based on 10-T or 12-T designs, are presented. Previous designs of 10-T adder are used in this paper for comparison purposes (Figure 1). The SERF adder [3], the Yuke Wang’s three 10-T adders (named: 9A, 9B, and 13A) [1], and Junming’s 10-T 1-bit adder [4]. They all suffer from 2V T loss of the output voltage levels for certain input signals sets. This was not critical for 0.35μm and older CMOS technologies. However, for the 0.18 μm and subsequent CMOS technologies, the proper operation of these adder designs is not possible including their use in n-bit adders. The voltage level degradation (V T loss) occurs when either the PMOS transistor is passing logic “0” (V TP loss) or the NMOS transistor is passing logic “1” (V TN loss). Fig. 1 shows some of existing 10T adders with the input signals set that causes 2V loss of its output signal. Two designs of 10-T full adder, with only one V T loss of the output voltage levels, are described and simulated in this paper. The critical part of the design is having a full swing XOR or XNOR gate in the first module to design the rest of the 1-bit adder with multiplexers to generate the C OUT and SUM outputs with improved voltage levels (Figure 2). To generate a full swing XOR gate signal in n-10T adder (fig. 2a), an inverter is used. The XOR-gate output and C IN input signals, both with full voltage swing, will be used as control signals in the following multiplexer stages to generate C OUT and SUM outputs with a maximum of one V T loss. Similarly, an inverter is used in the second design (fig. 2b). The Power dissipation of the two 10-T adders may further be reduced if the leakage current of the inverter is suppressed or decreased. The output signal of XOR gate, for the P-10T adder, is |V TP | for a specific input signals set (A=B=0). This causes the NMOS transistor of the inverter not to be completely turned off, giving rise to an unwanted leakage current and higher power dissipation. This also applies to the N-10T transistor when the input signals A and B are high. This problem is illustrated in Figure 3. Sizing the transistors to have a skewed inverter, such that the switching voltage (V S ) of the inverter in the P-10T adder is higher than 0.5 V DD , while it is lower in the N-10T adder. Furthermore, adding a narrow series-connected transistor to the inverter decreases the leakage current. (This technique is targeting the 0.13μm and subsequent CMOS technologies to reduce static power dissipation). This transistor is an NMOS for P-10T adder and a PMOS for N-10T adder. Figure 4 shows adding the series-connected transistor to the inverter. The inverter, used in the P-10T adder, may have an input of V TP in the worst case. This makes the n-MOS transistor not completely off. With sizing (W N =300nm, W P = 900nm) of the inverter transistors, the switching voltage is changed to V S =0.86V. Adding an n-MOS stack transistor, the switching voltage further increases to Vs=0.97V. For the N-10T adder, the input of its inverter degrades to V DD - V TN in the worse case. This makes the p-MOS transistor not completely off. With sizing (W N =600nm, W P = 300nm), the switching voltage decreases to Vs= 0.67V. Adding a p-MOS stack transistor, Vs further decreases to 0.63V. The power dissipation and the time delay of the two sized 10-T adders, the two adders with an extra transistor, CMOS (28T), and Transmission Gate Adder ( TGA 20T ) are simulated. The maximum frequency of input signals is 100MHz. The simulation results, in Table 1, show that both the power consumption and the Time delay of both P-10T and P-11T are higher than those of N-10T and N-11T. Therefore, we use N- 10T adder in the n-bit adders and the modified N-12T adder in the array multiplier as described in the next sections. One of the advantages of N-10T adder is that it can operate properly even when one of the inputs of XNOR gate has one V T loss. By applying the signal with one V T loss to input B, fig. 2, the V T loss does not propagate to the output of the adder, and consequently does not accumulate when used in n-bit Adders. The wave shown in figure 5 illustrates the full swing wave, called “A” [0, V DD ], and the wave with one V T loss, called “B” [V TP , V DD - V TN ], can be added together in the N- 10T adder. The output of XOR, after the inverter, is not affected by the V T loss of one of its two inputs. The input B, in the simulation, varied from 0.6 V to 1.2V representing the threshold-voltage loss of the signal level. However, this is quite larger than the value of the threshold- voltage with no body effect (V TN0 = 0.487V) in 0.18 μm CMOS technology. These values reflect the voltage levels obtained from the circuit simulation. This is due to the high body effect of the transistors. The V T loss can be reduced by using lower V T and/or lower-body-effect transistors, if accommodated by the adopted CMOS technology. Therefore, the described N-10T design can be used in n-bit RCA and CSA Adders [5] if the carry-out (C OUT ) of previous adder is applied at input B . However, this is not desirable for RCA adders since the path of the propagation of the carry signal is made longer. All the inputs signals are applied through buffers and have been fed into the adder cells, while all the outputs are loaded with buffer circuits. The power consumption and maximum time-delay values of the 4-bit and 12-bit adders are shown in Table 3. The simulation was carried out at a frequency of 50MHz for the 4-bit RCA and the 12-Bit CSA. Previous 12-T adders [2] do not operate correctly when used in a multiplier due to accumulation of V T loss, causing erroneous or ambiguous output logic value. Here we present a solution by modifying the design of the 10-T adders. One of the adder two outputs must have full voltage swing while the other can have a maximum of one V T loss. Adding two transistors to the multiplexer, used to generate C OUT , in the 10- T adders, allows a full voltage swing of C OUT . This increases the number of transistors of the improved adder to 12 (fig. 6). The 4x4 multiplier employs AND gates and an array of 12- T 1-bit adders to generate the final result [5-6]. The simulation is performed at a frequency of 50 MHz, for 0.18μm CMOS technology. The results are presented in Table 2 and some of the Output waves with one input wave are shown in figure 7. Minimum-Number-Transistor adders and multiplier which have up to one V T loss at their output signals are described in this paper. Two n-bit adders and one array-multiplier, with acceptable operation, were designed and simulated using the lowest-number-of-transistors (10-T and 12-T) full adders. Challenges in lowering the power dissipation and further reducing the V T losses can be solved in 0.13 μ m and subsequent CMOS technologies where multi V T devices are provided. MOSFET Transistors with lower body effect will also reduce the V losses. This work was partially supported by Natural Sciences and Engineering Research Council of Canada ...
Context 2
... of digital Integrated Circuits for many applications relies on three major criteria: Low power consumption, reduced chip area, and high speed. Using lower number of transistors to implement a logic function is beneficial in reducing the device and interconnect parasitic and reducing the chip area, resulting in lower time delay and potentially lower power consumption. However; the problem of threshold- voltage (V T ) loss of the output voltage levels, of those low- number-transistor circuits [2], may lead to faulty operation and higher leakage currents, especially for 0.18μm and subsequent CMOS technologies. Reducing the number of transistors of 1-bit adder design, for lower power consumption and higher speed in 0.35μm and older CMOS technologies was investigated [1-4]. However, many low-number-transistor adders do not operate correctly at low supply voltage in 0.18μm and subsequent CMOS technologies due to V T loss problem. The goal of this work is to design the lowest–number-of-transistors that can be used successfully in an n-bit adder or n-bit array multiplier. The targeted technology is 0.18μm CMOS Technology. This paper presents two 10-Transistor (10-T) and one 12-T Adder designs for n-bit adders and multiplier respectively. The two 10-T designs were not analyzed or studied before even though they were two of the forty-one 10-T adders mentioned in [2]. Adding one series-connected (stack) transistor to the circuit does reduce the power dissipation. The design of 12-T adders is reported here for the first time targeting their use in n- bit Multipliers. The two 10-T adders suffer from one V T loss instead of two V T as in many other designs [1], [3], [4]. The 12-T adder design has only one output (Sum) suffering from one V T loss while C OUT has full voltage swing. A 4-bit RCA, a 12-bit CSA adder, and a 4-bit Braun multiplier based on 10-T or 12-T designs, are presented. Previous designs of 10-T adder are used in this paper for comparison purposes (Figure 1). The SERF adder [3], the Yuke Wang’s three 10-T adders (named: 9A, 9B, and 13A) [1], and Junming’s 10-T 1-bit adder [4]. They all suffer from 2V T loss of the output voltage levels for certain input signals sets. This was not critical for 0.35μm and older CMOS technologies. However, for the 0.18 μm and subsequent CMOS technologies, the proper operation of these adder designs is not possible including their use in n-bit adders. The voltage level degradation (V T loss) occurs when either the PMOS transistor is passing logic “0” (V TP loss) or the NMOS transistor is passing logic “1” (V TN loss). Fig. 1 shows some of existing 10T adders with the input signals set that causes 2V loss of its output signal. Two designs of 10-T full adder, with only one V T loss of the output voltage levels, are described and simulated in this paper. The critical part of the design is having a full swing XOR or XNOR gate in the first module to design the rest of the 1-bit adder with multiplexers to generate the C OUT and SUM outputs with improved voltage levels (Figure 2). To generate a full swing XOR gate signal in n-10T adder (fig. 2a), an inverter is used. The XOR-gate output and C IN input signals, both with full voltage swing, will be used as control signals in the following multiplexer stages to generate C OUT and SUM outputs with a maximum of one V T loss. Similarly, an inverter is used in the second design (fig. 2b). The Power dissipation of the two 10-T adders may further be reduced if the leakage current of the inverter is suppressed or decreased. The output signal of XOR gate, for the P-10T adder, is |V TP | for a specific input signals set (A=B=0). This causes the NMOS transistor of the inverter not to be completely turned off, giving rise to an unwanted leakage current and higher power dissipation. This also applies to the N-10T transistor when the input signals A and B are high. This problem is illustrated in Figure 3. Sizing the transistors to have a skewed inverter, such that the switching voltage (V S ) of the inverter in the P-10T adder is higher than 0.5 V DD , while it is lower in the N-10T adder. Furthermore, adding a narrow series-connected transistor to the inverter decreases the leakage current. (This technique is targeting the 0.13μm and subsequent CMOS technologies to reduce static power dissipation). This transistor is an NMOS for P-10T adder and a PMOS for N-10T adder. Figure 4 shows adding the series-connected transistor to the inverter. The inverter, used in the P-10T adder, may have an input of V TP in the worst case. This makes the n-MOS transistor not completely off. With sizing (W N =300nm, W P = 900nm) of the inverter transistors, the switching voltage is changed to V S =0.86V. Adding an n-MOS stack transistor, the switching voltage further increases to Vs=0.97V. For the N-10T adder, the input of its inverter degrades to V DD - V TN in the worse case. This makes the p-MOS transistor not completely off. With sizing (W N =600nm, W P = 300nm), the switching voltage decreases to Vs= 0.67V. Adding a p-MOS stack transistor, Vs further decreases to 0.63V. The power dissipation and the time delay of the two sized 10-T adders, the two adders with an extra transistor, CMOS (28T), and Transmission Gate Adder ( TGA 20T ) are simulated. The maximum frequency of input signals is 100MHz. The simulation results, in Table 1, show that both the power consumption and the Time delay of both P-10T and P-11T are higher than those of N-10T and N-11T. Therefore, we use N- 10T adder in the n-bit adders and the modified N-12T adder in the array multiplier as described in the next sections. One of the advantages of N-10T adder is that it can operate properly even when one of the inputs of XNOR gate has one V T loss. By applying the signal with one V T loss to input B, fig. 2, the V T loss does not propagate to the output of the adder, and consequently does not accumulate when used in n-bit Adders. The wave shown in figure 5 illustrates the full swing wave, called “A” [0, V DD ], and the wave with one V T loss, called “B” [V TP , V DD - V TN ], can be added together in the N- 10T adder. The output of XOR, after the inverter, is not affected by the V T loss of one of its two inputs. The input B, in the simulation, varied from 0.6 V to 1.2V representing the threshold-voltage loss of the signal level. However, this is quite larger than the value of the threshold- voltage with no body effect (V TN0 = 0.487V) in 0.18 μm CMOS technology. These values reflect the voltage levels obtained from the circuit simulation. This is due to the high body effect of the transistors. The V T loss can be reduced by using lower V T and/or lower-body-effect transistors, if accommodated by the adopted CMOS technology. Therefore, the described N-10T design can be used in n-bit RCA and CSA Adders [5] if the carry-out (C OUT ) of previous adder is applied at input B . However, this is not desirable for RCA adders since the path of the propagation of the carry signal is made longer. All the inputs signals are applied through buffers and have been fed into the adder cells, while all the outputs are loaded with buffer circuits. The power consumption and maximum time-delay values of the 4-bit and 12-bit adders are shown in Table 3. The simulation was carried out at a frequency of 50MHz for the 4-bit RCA and the 12-Bit CSA. Previous 12-T adders [2] do not operate correctly when used in a multiplier due to accumulation of V T loss, causing erroneous or ambiguous output logic value. Here we present a solution by modifying the design of the 10-T adders. One of the adder two outputs must have full voltage swing while the other can have a maximum of one V T loss. Adding two transistors to the multiplexer, used to generate C OUT , in the 10- T adders, allows a full voltage swing of C OUT . This increases the number of transistors of the improved adder to 12 (fig. 6). The 4x4 multiplier employs AND gates and an array of 12- T 1-bit adders to generate the final result [5-6]. The simulation is performed at a frequency of 50 MHz, for 0.18μm CMOS technology. The results are presented in Table 2 and some of the Output waves with one input wave are shown in figure 7. Minimum-Number-Transistor adders and multiplier which have up to one V T loss at their output signals are described in this paper. Two n-bit adders and one array-multiplier, with acceptable operation, were designed and simulated using the lowest-number-of-transistors (10-T and 12-T) full adders. Challenges in lowering the power dissipation and further reducing the V T losses can be solved in 0.13 μ m and subsequent CMOS technologies where multi V T devices are provided. MOSFET Transistors with lower body effect will also reduce the V losses. This work was partially supported by Natural Sciences and Engineering Research Council of Canada ...
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Citations
... The last full adder designed is N10T. Because it has minimum number of transistors, it has the best performance and consumption area [13]. The limitation of CMOS transistors can be solved by CNFET. ...
... Power consumption and delay of these simulations are shown Figures 8 and 9. In the two chirality vectors, when chirality vectors are (15,0) and (13,0), the power consumptions are very high, at approximately 7.09E watt, so I try to eliminate from the Figure 8. The power consumption is decreased by decreasing the first chirality vector, 1 n but there is not any order in changing the delay. ...
... Vachhani Khyati [2] [6] made an attempt in implementing low power high speed full adder with only 10 transistors as shown in figure 2, giving highly appreciable results in terms of both delay and power. Omid Kavehei [9] et al., discussed shows the outstanding results with respect to low power implementing with only 10 transistors by applying a novel Gate Diffusion Input Technique (GDI). ...
In Modern VSLI technology, the systems with high speed and lower power processors plays vital role. Any hardware which involves computation technique, if processor is a heart of the system, then the Arithmetic Logic Unit is considered to be a brain of the system. The major computation is with respect to addition and hence full adders are the basic building blocks for any computation. Full-adders are also core element of the complex arithmetic circuits like addition, multiplication, division and exponentiation. Regarding to this importance, a new idea and investigations for constructing full-adders are required. The full adder with technique called Gate-Diffusion Input (GDI) Technique and GDITL based full adder cell for active low output contains 12 Transistors and consumes less power compared to other full adder cells. In this paper, attempt is made in implementing a novel, low power high performance CMOS 1-bit full-adder using Threshold Logic technique, which contains 10 transistors and three capacitors to implement Threshold Logic. In comparison with GDI Technique based full adder cell, the full adder cell with threshold logic has better performance. The performance is evaluated by calculating the Power Delay Product (PDP), which is the product of average power consumption and worst case delay. Further an attempt is made to design a CMOS 1-bit full-adder cell by combining both GDI technique and Threshold Logic technique and named it as GDITL Technique. This provides very low PDP compared to above mentioned full adder cells. Results and simulations demonstrate that the proposed design leads to an efficient full-adder in terms of power consumption, delay and area in comparison to well-known conventional full-adder designs.
... ign goal is to optimize for low power consumption. Digital hearing aids frequently employ the concept of filter banks whose complexity of computation requires more number of multiplications of higher power consumption. Therefore the construction of filter bank in Digital hearing aid with minimum number of multiplications is a desired design option. [11] Booth Wallace multiplier is used for implementing digital signal processing algorithms in hearing aids for low power consumption. ...
We present a new design for a 1-bit full adder featuring hybrid-CMOS design style. Our approach achieves low-energy operations in 90nm technology. Hybrid-CMOS design style makes use of various CMOS logic style circuits to build new full adders with desired specifications. The new SERF-full adder (FA) circuit optimized for ultra low power operation is based on modified XOR gates with clock gating to minimize the power consumption. And also generates full-swing outputs simultaneously. The new full-adder circuit successfully operates at low voltages with excellent signal integrity. The new adder displayed better power and delay metrics as compared to the standard full adders. To evaluate the performance of the new full adder in a real circuit, we realized 4-2,5-2,5-3,7-2,11-2,15-4,31-5 compressors which are basically used in multiplier modules of DSP filters. Simulated results using 90nm standarad CMOS technology are provided. The simulation results show a 5% -20% reduction in power and delay for frequency 50MHz and supply voltages range of 1.1 v.
... The simulation results demonstrate that the proposed full adder can be a better alternative for the low power applications and they can be used as a buil ding block in compressor, multiplier and multiple and accumulate units that are used in DSP chips. [14] ...
... than the proposed circuit due to the intermediate node concept. The proposed circuit gives 89.95%, 82.82% and 98.27% better performance compared to Fartash et al. [20], P-10T, 78.87%, 75.97% and 94.92% better performance than Fartash et al. [20], N-10T, 86.50%, 83.29% and 97.74% better performance than Fartash et al. [20], P11-T, 77.09%, 76.30% and 94.57% better performance than Fartash et al. [20], N-11T circuits for 0.18 µm feature size for power, delay and PDP respectively due to the complex design of the circuits.Table 3 ...
... than the proposed circuit due to the intermediate node concept. The proposed circuit gives 89.95%, 82.82% and 98.27% better performance compared to Fartash et al. [20], P-10T, 78.87%, 75.97% and 94.92% better performance than Fartash et al. [20], N-10T, 86.50%, 83.29% and 97.74% better performance than Fartash et al. [20], P11-T, 77.09%, 76.30% and 94.57% better performance than Fartash et al. [20], N-11T circuits for 0.18 µm feature size for power, delay and PDP respectively due to the complex design of the circuits.Table 3 ...
... than the proposed circuit due to the intermediate node concept. The proposed circuit gives 89.95%, 82.82% and 98.27% better performance compared to Fartash et al. [20], P-10T, 78.87%, 75.97% and 94.92% better performance than Fartash et al. [20], N-10T, 86.50%, 83.29% and 97.74% better performance than Fartash et al. [20], P11-T, 77.09%, 76.30% and 94.57% better performance than Fartash et al. [20], N-11T circuits for 0.18 µm feature size for power, delay and PDP respectively due to the complex design of the circuits.Table 3 ...
This paper presents a novel high-speed and high-performance multiplexer based full adder cell for low-power applications. The proposed full adder is composed of two separate modules with identical hardware configurations that generate Sum and Carry signals in a parallel manner. The proposed adder circuit has an advantage in terms of short critical path when compared with various existing previous designs. Comprehensive experiments were performed in various situations to evaluate the performance of the proposed design. Simulations were performed by Microwind 2 VLSI CAD tool for LVS and BSIM 4 for parametric analysis of various feature sizes. The simulation results demonstrate clearly the improvement of the proposed design in terms of lower power dissipation, less propagation delay, less occupying area and low power delay product (PDP) compared to other widely used existing full adder circuits.
... The proposed circuit gives 89.95%, 82.82% and 98.27% better performance compared to Fartash et al. [20], P-10T, 78.87%, 75.97% and 94.92% better performance than Fartash et al. [20], N-10T, 86.50%, 83.29% and 97.74% better performance than Fartash et al. [20], P11-T, 77.09%, 76.30% and 94.57% better performance than Fartash et al. [20], N-11T circuits for 0.18 µm feature size for power, delay and PDP respectively due to the complex design of the circuits. The area comparison of the proposed adder circuit with the published authors' adders is shown in Table 3Table 3 ...
... The proposed circuit gives 89.95%, 82.82% and 98.27% better performance compared to Fartash et al. [20], P-10T, 78.87%, 75.97% and 94.92% better performance than Fartash et al. [20], N-10T, 86.50%, 83.29% and 97.74% better performance than Fartash et al. [20], P11-T, 77.09%, 76.30% and 94.57% better performance than Fartash et al. [20], N-11T circuits for 0.18 µm feature size for power, delay and PDP respectively due to the complex design of the circuits. The area comparison of the proposed adder circuit with the published authors' adders is shown in Table 3Table 3 ...
... The proposed circuit gives 89.95%, 82.82% and 98.27% better performance compared to Fartash et al. [20], P-10T, 78.87%, 75.97% and 94.92% better performance than Fartash et al. [20], N-10T, 86.50%, 83.29% and 97.74% better performance than Fartash et al. [20], P11-T, 77.09%, 76.30% and 94.57% better performance than Fartash et al. [20], N-11T circuits for 0.18 µm feature size for power, delay and PDP respectively due to the complex design of the circuits. The area comparison of the proposed adder circuit with the published authors' adders is shown in Table 3Table 3 ...
This paper presents a novel high-speed and high-performance multiplexer based full adder cell for low-power applications. The proposed full adder is composed of two separate modules with identical hardware configurations that generate Sum and Carry signals in a parallel manner. The proposed adder circuit has an
advantage in terms of short critical path when compared with various existing previous designs. Comprehensive experiments were performed in various situations to evaluate the performance of the proposed design. Simulations were performed by Microwind 2 VLSI CAD tool for LVS and BSIM 4 for parametric
analysis of various feature sizes. The simulation results demonstrate clearly the improvement of the proposed design in terms of lower power dissipation, less propagation delay, less occupying area and low power delay product (PDP) compared to other widely used existing full adder circuits.
... The usage of adder cells in various applications has made many researchers excited to propose several kinds of logic styles for adder cells or improve the previous ones [3][4][5][6][7][8][9][10]. ...
... It is composed of two NMOS pass-transistor networks [3]. • The N-10T Full Adder cell which has 10 transistors and is based on XNOR/XOR signals [4]. • The CLRCL adder block, which has 12 transistors [6], and is based on pass-transistor logic. ...
This paper presents improved modified version of three low complexity 1-bit Full
Adder cells (CPL, N-10T, CLRCL), and also an additional design for CLRCL 1-bit Full
Adder cell, using Carbon Nano-Tube Field Effect Transistor (CNTFET) technology. These
designs benefit from higher computing speed, lower operating voltage, lower energy
consumption, less Vth loss in circuit nodes, and full swing results. The entire mentioned
peer MOSFET 1-bit Full Adders suffer from non full swing internal and output nodes and
poor driving capability. Using CNTFET technology significantly improves the swing
voltages and leads to full swing results, due to the ability of setting threshold voltage
according to our requirements nearly. All Full Adders are simulated with HSPICE using
32nm MOSFET and CNTFET technologies at several supply voltages ranging from 0.8V
down to 0.5V for comparison. Simulation results show great improvement in terms of delay
and power consumption compared to traditional MOSFET implementations.
... Proper level restoring technique with the inverter is used to solve the multiple threshold voltage fit losses problem in the carry propagate chain. The N-12T full-adder [6] generates its Sum and C OUI outputs using the pass-transistor logic style. The advantage of this full-adder is that the fit loss does not propagate to the output even if the inputs of the XNOR gates suffer a fit loss when it is applied to input B. Circuit diagrams of the fulladder just described are all presented inFigure I. ...
... B~:::::'--=L--W-W (e) N-I2T Full-adder [6] Figure I. Low-power full-adder cells. ...
Addition is an essential function in fundamental arithmetic operations. It is also the most copiously used operation in application-specific processors and digital signal processing application (DSP). In this paper, we propose a novel 17-transistors full-adder based on the N-12T full-adder, which P has a maximum of one threshold voltage (V<sub>t</sub>) degradation for output voltage levels. The performance of the proposed full-adder is compared against other low-power full-adder via extensive HSPICE simulation using 100 random input vectors. The simulation results show that the proposed design permits the use of lower operating voltage to derive lower power consumption and hence, the power delay product (PDP). The advantages of the proposed full-adder has been evaluated by integrating the proposed full-adder into a multiplier-less finite impulse response (FIR) filter that is commonly used in the multirate filter bank for biomedical applications.
... These two factors put power consumption into pool of critical parameters of many VLSI circuits [13][14][15]. For this reason, design of low power, high speed adder has become one of the most essential and important research problems [16][17][18]. ...
... The proposed circuit is simulated for total power (static plus dynamic) consumption and delay. From simulated result, it is observed the proposed cell consumes more than 60% less power than N-10T [17] adder cell due to stack transistor but occupies larger area on the chip. II. ...
... The proposed full adder circuit as well as other reported circuits is simulated by using Microwind2 and Dsch2 tools for power consumption, area, and delay at 120nm and 70nm technologies with appropriate supply voltages and the results are given in Table 1. The proposed 1 bit adder cell consumes lower power compared to other reported circuits and also gives faster response for carry out but occupies larger space on the chip and degrades sum output response compared to SERF [16], Junming [4] and P-11T [17] (see table 1). The maximum power saving is reported to be 63.5% at 120nm and 59% at 70nm compared to N-10T at cost of less than 10% area overhead. ...
This paper presents an improved circuit design of low power 1-bit full adder circuit. The circuit is designed and implemented based on top-down approach using total number of 10 transistors, thereby, known as 10-T cell. After simulation of the circuit, a clear view of the circuit performance, in terms of power, delay, area was studied. The performance of the proposed circuit was compared with other reported circuits in various literatures and observed approximately more than 60% reduction in power consumption. The proposed cell gives faster response for the carry output and can be used at higher temperature with minimal power loss. The drawback of the circuit is that it occupies larger area on the chip.
... Actually, the best criterion for comparison is Power Delay Product (PDP). Considering PDP criteria, the proposed circuit is extremely better than FA proposed in [16], which has a better power consumption than new proposed circuit. By the way, to have a better view of different aspects of proposed circuit and other works, numerical results, comparisons and improvements are inserted inTable IV. ...
... It can be easily seen that in all cases new proposed hybrid analog-digital circuit could improve predecessor full adders in delay, power consumption and PDP criteria. The only exception is the power consumption respecting to that one proposed in [16], in which the power consumption of proposed circuit was 33.7% worse than [16] while the delay has been 544% improved. Hence, the accomplished speed compensates the lost in power consumption and referring to PDP criteria, again a 326% improvement has been gained. ...
... It can be easily seen that in all cases new proposed hybrid analog-digital circuit could improve predecessor full adders in delay, power consumption and PDP criteria. The only exception is the power consumption respecting to that one proposed in [16], in which the power consumption of proposed circuit was 33.7% worse than [16] while the delay has been 544% improved. Hence, the accomplished speed compensates the lost in power consumption and referring to PDP criteria, again a 326% improvement has been gained. ...
In this paper a new high speed and low power adder is presented. The circuit uses a hybrid concept of analog and digital circuit design to propagate the carry and so achieve a Full Adder with 78 ps delay and 7.26 muW of power consumption. SPICE Simulations performed on the 0.18 mum TSMC Technology demonstrates the average improvement of 159%, 184% and 516%, respectively for delay, power consumption and PDP.
