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This work presents the design and the test results of an analog decoder for the 40-bit block length, rate 1/3, Turbo Code defined in the UMTS standard. The prototype is fully integrated in a three-metal double-poly 0.35-μm CMOS technology, and includes an I/O interface that maximizes the decoder throughput. After the successful implementation of pr...
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... groups. Tutorial explanations of the Turbo prin- ciple and the analog decoding approach can be found in [13] and [5], [14], respectively. Here, we will give just a brief out- line of the working principle of a Turbo decoder and of the difference between its digital and analog implementation. Con- sider the Turbo decoder block diagram reported in Fig. 2. The decoding is done by the two soft-input-soft-output (SISO) de- coders [15], each matched to one of the constituent encoders in Fig. 1. They use and exchange soft information as an index of the reliability of the received symbols and of their a posteriori estimate of the original information bits . The two sources of soft ...
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... iterative exchange of information (Turbo prin- ciple) that yields a dramatic gain in the error-correcting perfor- mance of the decoder [8]. The exchange is fruitful because the parity check streams, and , generated by the two constituent encoders, are only weakly correlated thanks to the interleaver. The interleavers ( ) and de-interleavers in Fig. 2 make sure that the two SISO decoders process the soft information in the correct spatial order. Finally, the a posteriori probabilities coming from the two SISO decoders are combined and then a hard decision is made (see Fig. 2). The SISO decoders implement the maximum a posteriori (MAP) decision rule using the forward-backward ...
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... constituent encoders, are only weakly correlated thanks to the interleaver. The interleavers ( ) and de-interleavers in Fig. 2 make sure that the two SISO decoders process the soft information in the correct spatial order. Finally, the a posteriori probabilities coming from the two SISO decoders are combined and then a hard decision is made (see Fig. 2). The SISO decoders implement the maximum a posteriori (MAP) decision rule using the forward-backward algorithm (a.k.a. BCJR algorithm). For the details of the algorithm, we refer the interested reader to [15]- [17]. In its multiplicative version, the algorithm performs sum-of-product computations on bit probabilities in the forward ...
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Citations
... The key driver behind the success of LDPC is the use of iterative message-passing algorithms [3], which are powerful decoding algorithms with a manageable complexity. The iterative decoding algorithms are scalable, and hence can be efficiently implemented using digital [4], [5] and analog [6], [7] approaches. The motivation to use analog circuits for decoding is based on lower power dissipation and faster processing speed than the digital design [8], [9]. ...
The analog low-density parity-check (LDPC) decoder, which is a specific application of the probabilistic computing, is considered to be a promising solution for powerconstrained applications. However, due to the lack of efficient electronic design automation tools and reliable circuit model, the analog LDPC decoders suffer from costly hand-craft design cycle, and are unable to provide enough coding gains for practical applications. In this paper, we present an implementation of a (480,240) CMOS analog LDPC decoder, which is the longest implemented code to date using the analog approach. We first propose an analog LDPC decoder architecture, which is constructed by the reusable modules and can significantly reduce the hardware complexity. And then we present a mixed behavioral and structural model for the analog LDPC decoding circuits, which can reliably and efficiently predict the error-correcting performance. Finally, the experimental results show that the decoder prototype, which is fabricated in a 0.35-μm CMOS technology, can achieve a throughput higher than 50Mbps with the power consumption of 86.3mW for the decoder core, and can offer a superior 6.3dB coding gain at the bit error rate of 10-6 when the tested throughput is 5Mbps. The proposed analog LDPC decoder is suitable for the power-limited applications with moderate throughput and certain coding gains.
... Note that a number of parallel turbo decoders have been proposed previously, and most of them mainly tried to improve the level of parallelism in order to get a higher throughput and lower latency. In [18], a fully-parallel turbo decoder was implemented using analog decoder, but only short message lengths are supported. According to [19], a parallel turbo decoder algorithm that operates on the basis of stochastic bit sequences was proposed which requires more processing time than Log-BCJR algorithm. ...
As a class of high-performance forward error correction codes, turbo codes, which can approach the channel capacity, could become a candidate of the coding methods in future terrestrial broadcasting (TB) systems. Among all the demands of future TB system, high throughput and low latency are two basic requirements that need to be met. Parallel turbo decoding is a very effective method to reduce the latency and improve the throughput in the decoding stage. In this paper, a parallel turbo decoder is designed and implemented in field-programmable gate array (FPGA). A reverse address generator is proposed to reduce the complexity of interleaver and also the iteration time. A practical method of modulo operation is realized in FPGA which can save computing resources compared with using division operation. The latency of parallel turbo decoder after implementation can be as low as 23.2 us at a clock rate of 250 MHz and the throughput can reach up to 6.92 Gbps.
... However, this approach only works for a very limited set of turbo code designs, which does not include those employed by any standards. A fully-parallel turbo decoder implementation that represents the soft information using analogue currents was proposed in [15], however it only supports very short message lengths N . Similarly, [16] proposes a fully-parallel turbo decoder algorithm that operates on the basis of stochastic bit sequences. ...
This paper proposes a novel alternative to the Logarithmic Bahl-Cocke-Jelinek-Raviv (Log-BCJR) algorithm for turbo decoding, yielding significantly improved processing throughput and latency. While the Log-BCJR processes turbo-encoded bits in a serial forwards-backwards manner, the proposed algorithm operates in a fully-parallel manner, processing all bits in both components of the turbo code at the same time. The proposed algorithm is compatible with all turbo codes, including those of the LTE and WiMAX standards. These standardized codes employ odd-even interleavers, facilitating a novel technique for reducing the complexity of the proposed algorithm by 50%. More specifically, odd-even interleavers allow the proposed algorithm to alternate between processing the odd-indexed bits of the first component code at the same time as the even-indexed bits of the second component, and vice-versa. Furthermore, the proposed fully-parallel algorithm is shown to converge to the same error correction performance as the state-of-the-art turbo decoding algorithm. Owing to its significantly increased parallelism, the proposed algorithm facilitates throughputs and latencies that are up to 6.86 times superior to those of the state-of-the art algorithm, when employed for the LTE and WiMAX turbo codes. However, this is achieved at the cost of a moderately increased computational complexity and resource requirement.
... Reducing this number requires use of bit-serial arithmetic [11], [12] or stochastic computational techniques [13], [14]. Simulation and implementation of small analog decoders have shown promising results in terms of energy efficiency or throughput [15][16][17][18][19][20][21][22][23][24][25][26][27][28]. While analog implementations of the computational primitives are elegant, they suffer from physical non-idealities such as mismatch, thermal noise and short-channel effects. ...
Analog implementations of digital error control decoders, generally referred to as analog decoding, have recently been proposed as an energy and area competitive methodology. Despite several successful implementations of small analog error control decoders, little is currently known about how this methodology scales to smaller process technologies and copes with the non-idealities of nano-scale transistor sizing. A comprehensive analysis of the potential of sub-threshold analog decoding is examined in this paper. It is shown that mismatch effects dominated by threshold mismatch impose firm lower limits on the sizes of transistors. The effect of various forms of leakage currents is also investigated and minimal leakage current to normalizing currents are found using density evolution and control simulations. Finally, the convergence speed of analog decoders is examined via a density evolution approach. The results are compiled and predictions are given which show that process scaling below 90 nm processes brings no advantages, and, in some cases, may even degrade performance or increase required resources.
... When considering complex decoders, there is a relatively large discrepancy, from a few hundredths [12] up to a couple of dBs [13], between the two. As most of the published work to date concerns the design of CMOS analog decoders [14] - [17], the performance degradations in terms of BER brought in by MOS transistors imperfections such as mismatches have been studied, see for instance [17]. Fewer works have been published on BJT-based analog decoders [4] [12] [18]. ...
... When considering complex decoders, there is a relatively large discrepancy, from a few hundredths [12] up to a couple of dBs [13], between the two. As most of the published work to date concerns the design of CMOS analog decoders [14] - [17], the performance degradations in terms of BER brought in by MOS transistors imperfections such as mismatches have been studied, see for instance [17]. Fewer works have been published on BJT-based analog decoders [4] [12] [18]. ...
This paper presents the effect of bipolar junction transistors' (BJTs) parasitic elements on the decoding performance of a BiCMOS analog decoder. The transistors' parasitic effects are taken into account to develop a more accurate behavioral model of the computing nodes. The model is applied to double-binary 0.25-mum BiCMOS analog decoders. Behavioral simulations show that the BJTs' parasitic elements deteriorate the error-correcting performance of a stand-alone a posteriori probability (APP) decoder by 0.5 dB compared with the ideal bit error rate (BER). In a turbo scheme, the loss is reduced to 0.2 dB for a BER that is smaller than 10<sup>-2</sup>. A simple solution based on an nMOS amplifier is proposed to counterbalance the dominant parasitic element. The amplifier reduces the degradation by 0.2 dB for the APP decoder. However, the turbo decoder is improved only for a BER above 10<sup>-2</sup>.
... Besides the usual digital implementation of turbo and LDPC decoders, some research has shown the feasibility of implementing them using analog networks to fully exploit the information available from the channel [1]- [4]. These theoretical works were followed by fully operational prototypes using either sub-threshold-biased CMOS [5]- [8] or forward-biased bipolar transistors [9], [10] to build the computing cells. The main advantage of such analog implementations is that the analog network does not require any scheduling, meaning that the network converges to a stable state corresponding to the code word. ...
... However, for these frame lengths, it is well known that turbo and LDPC codes are not at their best [12]. There are many applications requiring such short codes and for which analog decoding can be of interest if codes other than turbo and LDPC are used, such as sensor networks and volatile A Subthreshold PMOS Analog Cortex Decoder for the (8,4,4) ...
... This paper proposes a graph-based decoding structure which lends itself to an analog implementation. The background of the study is the (8,4,4) extended Hamming code because it is a simple and short code. A proof-of-concept Cortex analog decoder for this code is designed, tested, and compared to its equivalent LDPC-like decoder. ...
This paper presents a method for decoding high minimal distance () short codes, termed Cortex codes. These codes are systematic block codes of rate 1/2 and can have higher than turbo codes. Despite this characteristic, these codes have been impossible to decode with good performance because, to reach high , several encoding stages are connected through interleavers. This generates a large number of hidden variables and increases the complexity of the scheduling and initialization. However, the structure of the encoder is well suited for analog decoding. A proof-of-concept Cortex decoder for the (8, 4, 4) Hamming code is implemented in subthreshold 0.25- CMOS. It outperforms an equivalent LDPC-like decoder by 1 dB at BER= and is 44 percent smaller and consumes 28 percent less energy per decoded bit.
... Similarly, the mismatch in the four-FFT pictured in Fig. 7 can be derived. The following equation is obtained, which has the same form as (8) (9) where is in general in the form of . The mismatch model for the four-FFT thus has the same structure as for the two-FFT, and the only differences are the coefficients in the model. ...
An N -symbol discrete Fourier transform ( N -DFT) processor based on analog CMOS current mirrors that operate in the strong inversion region is presented. It is shown that transistor mismatch can be modeled as an input-referred noise source that can be used in system-level studies. Simulations of a radix-2, 256-symbol fast Fourier transform (FFT) show that the model produces equivalent results to those of a model that incorporates a mismatch term into each current mirror. It is shown that in general, high-radix FFT structures and specifically the full-radix DFT have reduced sensitivity to mismatch and a reduced number of current mirrors compared to radix-2 structures and have some key advantages in terms of transistor count with respect to comparable digital implementations. Simulations of an orthogonal frequency-division multiplexing system with forward error control coding, that take into account current mirror nonidealities such as mismatch, show that an analog DFT front end loses only 0.5 dB with respect to an ideal circuit.
... Conventional LDPC decoding algorithms are either based on the sum-product formulation [3], [4] or are based on suboptimal approximation techniques such as the min-sum (MS) formulation [5]. Both of these approaches are soft-decision algorithms that operate either in probability or log-likelihood ratio (LLR) domain [5] and have been successfully implemented using analog and digital hardware [6]- [11], [14]. In particular, analog decoders are attractive as compared to their digital counterparts because they exploit computational primitives inherent in device physics to achieve high energy efficiency [16]. ...
A margin propagation (MP) algorithm that can be used for implementing analog decoders for low-density parity check (LDPC) codes is presented. Unlike conventional sum-product analog decoders that rely on translinear operation of transistors, MP decoders use addition, subtraction and threshold operations, and therefore can be mapped onto different analog circuit topologies (current-mode, charge-mode, or nonelectronic circuits). This brief describes salient properties of the MP decoding algorithm and compares its performance to the sum-product and the min-sum (MS) decoding algorithms. Simulation results demonstrate that MP based LDPC decoders achieve nearly an identical bit error rate performance as their sum-product counterparts and achieve superior performance as compared to the MS decoding algorithm. Results presented in this brief also demonstrate that, when messages in LDPC decoding are corrupted by additive noise, the MP decoding algorithm delivers superior performance compared to its sum-product and MS counterparts.
... On the other hand, recent progress in analog decoding has proven that the MAP algorithm can be naturally mapped onto analog translinear networks [4,5] outperforming digital decoding due to a significant improvement of the power/speed ratio with only a negligible loss regarding the error correction capability. So far, several implementations of analog channel decoders in CMOS and BiCMOS technologies have been reported in the literature as a proof-ofconcept [6][7][8][9][10]. Research groups have mostly focused on the procedure to decrease drastically the power consumption in analog decoders, by using MOS transistors [7,9,10] which operate in subthreshold region, (so as to comply with the translinear principle), and gradually rejected the BiC-MOS technology, which was employed at the beginning. ...
... So far, several implementations of analog channel decoders in CMOS and BiCMOS technologies have been reported in the literature as a proof-ofconcept [6][7][8][9][10]. Research groups have mostly focused on the procedure to decrease drastically the power consumption in analog decoders, by using MOS transistors [7,9,10] which operate in subthreshold region, (so as to comply with the translinear principle), and gradually rejected the BiC-MOS technology, which was employed at the beginning. MOS transistors that work at the subthreshold region are able to comply with the required translinear principle in contrast to the case of operation at the region of strong inversion. ...
... MOS transistors that work at the subthreshold region are able to comply with the required translinear principle in contrast to the case of operation at the region of strong inversion. Although they consume less power than bipolar transistors, they are quite slower and more sensitive to process variations [7,10,11,14]. Despite the achievable low-power consumption, only low to moderate throughput can be accomplished with the analog channel decoders implemented in CMOS processes while the adoption of SiGe BiCMOS technology might lead to a quite higher decoding speed for moderate power consumption, thus making it suitable for high-speed telecom applications. ...
Although recent implementations of analog iterative decoders have proven their potential for higher decoding speed and less
power consumption than their digital counterparts, the CMOS or conventional BiCMOS technologies used so far seem to be incapable
to cope with the need for high throughput that high-speed applications require. Within this context this work presents the
design and test results of a high-speed analog SISO (Soft-Input Soft-Output) channel decoder for an 8-bit trellis code by
exploiting the high-speed features of SiGe heterojunction bipolar transistors (HBTs). It is one of the first successful implementations
of an error-correcting decoder in SiGe BiCMOS technology, which incorporates a high-speed I/O interface. A high-level model
of the mismatch effects indicates that there is no significant performance penalty. Moreover, simulations and performance
evaluations of an analog Turbo decoder based on the designed SISO decoder are provided. Even though the IC of the SISO module
was tested at a throughput up to 3Mbps, simulation results show that the decoder is capable to operate at 50Mbps. The measured
power consumption is 860mW and the die area is 3.4× 3mm2.
... This explains why most of the papers published so far deal with non-industrial codes. Only recently, three decoders have been proposed for industrial standards: UMTS (3GPP) in [1], IEEE 802.16a standard in [2] and DVB-RCS-like codes in [3]. Only the first two were implemented on chip and tested; the third one was only simulated. ...
Based on multiple-slice turbo codes, a novel semi-iterative analog turbo decoding algorithm and its corresponding decoder architecture are presented. This work paves the way for integrating flexible analog decoders dealing with frame lengths over thousands of bits. The algorithm benefits from a partially continuous exchange of extrinsic information to improve decoding speed and correction performance. The proposed algorithm and architecture are applied to design an analog decoder for double-binary codes. Taking full advantage of multiple slice codes, the on-chip area is shown to be reduced by ten when compared to a conventional fully parallelized analog slice turbo decoder. The reconfigurable analog core area for frames of 40 bits up to 2432 bits is 37 nm<sup>2</sup> in a 0.25-mum BiCMOS process.
