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A 1.2-V 72-Mb double data rate 3 (DDR3) SRAM achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits. Single-ended main data lines halve the data line precharging power dissipation and the number of data lines. Clocks phase shifted by 0°, 90°, and 270° are generated through the proposed clock adjustment circuits. The latter circuits...
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... systems. The 72-Mb SRAM is fabricated using a 0.1-m CMOS technology with the implemented SRAM, breaking the 1-m barrier for the cell size. Some papers have been published including six-transistor (6T) SRAM cells near the 1-m barrier [1]- [3]. One paper described a 6T embedded SRAM cell breaking the 1-m barrier with the cell size of 0.998 m [4]. Fig. 1 shows the trend in SRAM size recently reported. The implemented cell size of this work is 0.845 m , which is the smallest size to date. The chip size is 151.1 mm . To halve the data line precharging power dissipation and the number of data lines, single-ended main data lines (SMDLs) are designed using dynamic self-resetting circuits ...
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... the change in unit delay, resulting in a phase shift of 90 . The jitter of the clock shifted by 0 is 13 ps and that of the clock shifted by 90 is 40 ps. In addition, the amount of phase shift can be controlled by JTAG_CONT to trim the setup/hold time and the data valid window. The covered range of the phase shift by JTAG_CONT is 20 with 7 steps. Fig. 10 shows the test result of the proposed CAC. Two clocks phase shifted by 90 from the rising and falling edge of external clock are ...
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... stub causes relatively large reflections compared with on-chip termination due to the impedance mismatch. Therefore, on-chip termination is developed to remove the effect of the unterminated stub and improve signal integrity. An on-chip input termination of the center-tapped-termination (CTT) type is designed by using CMOS transistors. Fig. 11(a) shows the input termination scheme of data pad. The off-chip driver (OCD) is activated during the read operation and the ter- minator is activated during the write operation. The impedance of the OCD and the terminator is controlled by digital codes generated by two PICs with reference resistors RQ and RT [10]. In 72-Mb DDR3 SRAM, RQ ...
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... equal to the board characteristic impedance, and the input impedance of terminators in the data pads is 75 . Ter- mination impedance is not matched to the board characteristic impedance to reduce the dc current dissipated in the terminator. To reduce input capacitance, 1/5 of the OCD transistors are used as terminators during nonread operation. Fig. 11(b) and (c) shows the simplified schematic of the terminator for the data pad and the address/control/clock pad. The terminator for the data pads consists of transistor arrays of nMOS and diode-connected nMOS pairs for pulldown, and pMOS and diode-connected pMOS pairs for pullup. The terminator for address/control/clock pads is composed of ...
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... [10]. In the previously published approaches, the pulldown code is generated from the pullup code which has a quantization error [10]. As a result, the accuracy of the pulldown code is dependent upon the pullup code. To eliminate the dependency of the pulldown code on the pullup code, a new impedance code generation scheme is proposed. Fig. 12 shows the block diagram of the PIC. By feedback operation of AMP1 and a pMOS (M0), VZQ becomes VREF ( VDDQ ). The reference current of VREF/RQ flows through M0 and RQ. M3 copies the current in M0 to make pulldown impedance code and M1, M2, M4, and AMP2 copy the current in M0 to make pullup impedance code. Therefore, pulldown impedance ...
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... input impedance of terminator should be linear to main- tain equal channel environment for changing pad voltage and to improve the signal integrity and the input data valid windows in a system. Fig. 13(a) shows the linearity of an ideal terminator. In the ideal case, the relationship between pad voltage and input current is perfectly linear. But due to the nonlinear characteris- tics in transistors, there exists linearity error. Fig. 13(b) shows the linearity error of the terminator. The impedance of termi- nator is evaluated either by ...
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... for changing pad voltage and to improve the signal integrity and the input data valid windows in a system. Fig. 13(a) shows the linearity of an ideal terminator. In the ideal case, the relationship between pad voltage and input current is perfectly linear. But due to the nonlinear characteris- tics in transistors, there exists linearity error. Fig. 13(b) shows the linearity error of the terminator. The impedance of termi- nator is evaluated either by forcing a voltage to a pad and mea- suring the current flowing into a pad, or by measuring pullup impedance and pulldown impedance, respectively. Measuring pullup impedance and pulldown impedance, respectively, is just executed in test ...
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... 13(b) shows the linearity error of the terminator. The impedance of termi- nator is evaluated either by forcing a voltage to a pad and mea- suring the current flowing into a pad, or by measuring pullup impedance and pulldown impedance, respectively. Measuring pullup impedance and pulldown impedance, respectively, is just executed in test mode. Fig. 13(b) shows the result of forcing a voltage and measuring the current. The total linearity error of the terminator is 4.1% over PVT variations. The linearity error is measured between 0.3 and 1.2 V. Fig. 14 shows the eye diagram of the input data at a data rate of 1.5 Gb/s and a power supply of 1.5 V. In the case of no termination, the ...
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... impedance and pulldown impedance, respectively. Measuring pullup impedance and pulldown impedance, respectively, is just executed in test mode. Fig. 13(b) shows the result of forcing a voltage and measuring the current. The total linearity error of the terminator is 4.1% over PVT variations. The linearity error is measured between 0.3 and 1.2 V. Fig. 14 shows the eye diagram of the input data at a data rate of 1.5 Gb/s and a power supply of 1.5 V. In the case of no termination, the signal swing is larger than that in on-chip termination. But the noise and the reflections increase jitter and reduce the input data valid window. In the case of on-chip ter- mination, the signal swing is ...
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... wider input data valid window is obtained. The data input valid window with on-chip termination is 480 ps at 750 mV 200 mV when the terminator impedance and the board char- acteristic impedance is 75 and 25 , respectively. Included in the results are 10% PVT variations, 10% termination impedance variations, and system models. VI. HARDWARE RESULTS Fig. 15 shows the hardware results at a data rate of 1.5 Gb/s and 750-MHz core frequencies. K is the external clock of 750 MHz. Data (DQ0, DQ1) of 1.5 Gb/s is well aligned with the echo clock (CQ, CQb). DQ latency is 2.1 ns from the time that an address is captured. Fig. 16 shows the chip micrograph of the 72-Mb ...
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... 10% termination impedance variations, and system models. VI. HARDWARE RESULTS Fig. 15 shows the hardware results at a data rate of 1.5 Gb/s and 750-MHz core frequencies. K is the external clock of 750 MHz. Data (DQ0, DQ1) of 1.5 Gb/s is well aligned with the echo clock (CQ, CQb). DQ latency is 2.1 ns from the time that an address is captured. Fig. 16 shows the chip micrograph of the 72-Mb ...
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... A programmable impedance controller (PIC) creates the impedance codes, having as reference the external resistors R T and R Q for ODT and OCD, respectively. In [11] a 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM is described, which satisfies the need for high data rate and area density required in recent ultra fast systems together with the corresponding on-chip termination. In [12] the implementation of a third-generation 1.1-GHz 64-bit microprocessor is presented whereas it provides some details on the DDR1 SSTL I/O circuit solutions at the memory interface. ...
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