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This paper describes a 3.6-Gbps 27-mW transceiver for chip-to-chip applications. A novel data receiving and timing recovery technique are presented with very low power penalties while maintaining high signal integrity. The input comparator filters noise with built-in bandwidth control and digital offset compensation while consuming 300 uW. Static p...
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Context 1
... transmitter architecture is shown in Fig. 6. The input data is at 225 Mb/s to ease the system testing. A 16:1 multi- plexer serializes the input data into 3.6-Gb/s data at the output. The 16:1 multiplexer is a binary tree of 2:1 multiplexers. The clock signals that drive the multiplexers are 1.8 GHz, 900 MHz, 450 MHz, and 225 MHz. Each clock is divided down from a 1.8-GHz PLL ...
Context 2
... the eye is completely closed before equal- ization. After proper equalization, the eye opening is enlarged to 37 mV (height) and 189 ps (width). The two available taps limit the pre-emphasis performance. To measure the pre-em- phasis resolution, a DNL plot with respect to the filter coeffi- cient is measured. The maximum DNL of 0.8 LSB (shown in Fig. 26) indicates that any further increase in number of binary segments may not improve the pre-emphasis accuracy. Fig. 10 illustrates the measured output impedance along with simulated results. The figure shows that the output impedance maintains within 10% variation. The timing and voltage margin of the receiver, as shown in Fig. 27, is ...
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Citations
... The voltage-mode driver has one-quarter of the current consumption of the currentmode driver [3]. Utilizing low-swing voltage-mode drivers can reduce the static power consumption significantly [4]- [6]. Current-mode and voltage-mode driver topologies are shown in Figs. ...
... The inclusion of equalization at high data rates adds extra complexity and power consumption to the design [3]. In a segmented output driver for the equalization with N-bit resolution, 2 N -segmented output drivers are required, resulting more complexity and power consumption of the pre-driver [4]. A hybrid voltagemode driver with current-mode equalization can be used to eliminate 2 N -segmented output drivers, thereby reducing the complexity and power consumption of the pre-driver [5]. ...
In this paper, a modified structure for low-swing voltage-mode drivers in high-speed serial links is proposed, which offers lower static power and reduces the number of transistors compared to the conventional design. This structure adopts an impedance-modulated 2-tap equalizer with analog tap control. The impedance modulation technique is applied to only one input of the driver. Therefore, six transistors are eliminated in the driver and their control impedance circuitry is removed. Simulation results of an 8-Gb/s serial link in a 0.13-µm CMOS technology confirm that the proposed structure reduces the width of the transistors and the static power consumption by 20% and 11%, respectively. Also when a 200 mV p-p differential signal is sent over a channel with 10 dB attenuation at 4 GHz, the eye diagram of the received data has a 113.5 mV eye opening.
... Because the circuit bandwidth of an energyefficient CMOS circuit is a technology-defined parameter, power-hungry circuits such as a current-mode logic circuit are required when the clock frequency exceeds a certain limit. As the rule-of-thumb, the limit is at the clock period of four fanout-of-four CMOS inverter delay [7], [8]. On the other hand, the increased degree of parallelism results in increased hardware complexity, and therefore, the area and power efficiencies of the I/O transmitter are degraded. ...
... Stabilization capacitor C comp of 800 fF is used in this design, thereby, obtaining a phase margin of 63 @BULLET . Unlike conventional pre-emphasis tap implementations that require parallel slices at the output node [7], [12], a pre-emphasis tap is implemented in the predriver stage in the proposed transmitter. The output swing and the pre-emphasis coefficient are adjusted by changing the current flowing into the input of the output driver [I in in Fig. 4 (a)]. ...
An energy-efficient forwarded-clock transmitter that offers a scalable pre-emphasis equalization and output voltage swing is presented. A resistive-feedback inverter-based driver is used to overcome the drawbacks of the conventional drivers. Moreover, half-rate clocking structure is employed in order to minimize power consumption in 65-nm CMOS technology. The proposed transmitter consists of two data lanes, a shared clock lane, and a global impedance regulator. The prototype chip is fabricated in 65-nm CMOS technology and occupies an active area of 0.15 mm². The proposed transmitter achieves 100-250 mV single-ended swing and exhibits the energy efficiency of 1 pJ/bit at the per-pin data rate of 10 Gb/s.
... Especially, the clock buffer, which delivers the fastest signal to the largest load in the TX chip, dissipates a large amount of power. Therefore, parallel-clocking architecture, which is optimized to minimize the inter-chip clocking overhead, enhances the energy and area efficiencies of the TX [10], [11] . A fanoutof-four (FO4) CMOS inverter-chain, which provides minimal delay and energy efficiency to drive a certain capacitive load, can be used as the clock buffer at low clock frequencies. ...
This paper describes the design of a 10 GHz phase-locked loop (PLL) for a 40 Gb/s serial link transmitter (TX). A two-stage ring oscillator is used to provide a four-phase, 10 GHz clock for a quarter-rate TX. Several analyses and verification techniques, ranging from the clocking architectures for a 40 Gb/s TX to oscillation failures in a two-stage ring oscillator, are addressed in this paper. A tri-state-inverter-based frequency-divider and an AC-coupled clock-buffer are used for high-speed operations with minimal power and area overheads. The proposed 10 GHz PLL fabricated in the 65 nm CMOS technology occupies an active area of 0.009 mm² with an integrated-RMS-jitter of 414 fs from 10 kHz to 100 MHz while consuming 7.6 mW from a 1.2-V supply. The resulting figure-of-merit is -238.8 dB, which surpasses that of the state-of-the-art ring-PLLs by 4 dB.
... Especially, the clock buffer, which delivers the fastest signal to the largest load in the transmitter chip, dissipates a large amount of power. Therefore, parallel-clocking architecture, which is optimized to minimize the inter-chip clocking overhead, enhances the energy and area efficiencies of the transmitter [13], [14]. A fanout-of-four (FO4) CMOS inverter-chain, which provides minimal delay and energy efficiency to drive a certain capacitive load, can be used as the clock buffer at low clock frequencies. ...
... with a single oscillator is hard to cover the wide frequency range. Therefore, most of the wide-range transceiver designs employ multiple PLLs, or oscillators [13], [52], [55][57]. In this work, a voltage-mode (VM) transmitter which offers a controllable output swing and pre-emphasis as well as the scalable supply, while matching the output impedance, is presented. ...
... As a result, determining the clocking architecture of a transmitter is related to the base circuit topology. As shown in Fig. 3. 4, parallel clocking structure, such as a half-rate or a quarter-rate clocking, in return for the increased hardware complexity, offers lower clock frequency and relaxes the required circuit bandwidth [13], [14]. As a result, the main aspects that should be considered while building an energy-efficient wide range transmitter can be summarized as follows. ...
... Depending on the quality of the receiver and BER requirements, the voltage margin can change; however, any change in the voltage margin just scales the current/voltage requirement and does not significantly affect the optimization and the conclusions. For a current mode driver, the minimum current and power required at the transmitter are given by A technique to optimize the data-rate based on energy per bit is presented in [29] and [30]. However, these studies assume the aggregate bandwidth of the link to be fixed and hence do not put constraints on the total routing width available. ...
Frequency and time domain models are developed for backplane (BP), printed circuit board (PCB), and silicon interposer (SI) links using six-port transfer matrices (ABCD matrices) for bumps, vias and connectors, and coupled multiconductor transmission lines for traces. The six-port transfer matrix approach enables easy computation of the transfer function, as well as near-end and far-end crosstalk. The intersymbol interference is accounted for by computing the pulse response for the worst case bit pattern. Furthermore, the models developed here are used to optimize the data-rate and trace width for each of the links, so that the aggregate bandwidth obtained per joule of energy supplied to the link is maximized. The modeling and optimization approach developed here serves as a good platform to compare the air-gap interconnects against BP, PCB, and SI interconnects on lossy dielectrics. It is shown that air-gap interconnects can provide an aggregate bandwidth improvement of (3times ) – (4times ) for BP links at a comparable energy per bit, and a (5times ) – (9times ) improvement in aggregate bandwidth of PCB links at the expense of 20% higher energy per bit. For SI links, air-gap interconnects are shown to provide a (2times ) – (3times ) improvement in aggregate bandwidth and a (1times ) – (1.5times ) improvement in energy per bit.
... 2, are widely utilized in different serial links. Although current-mode drivers are mostcommonly used [3], the power wasted in the parallel termination led designers to consider low-swing voltage-mode drivers456. This paper focuses on low-swing voltage-mode driver technique and uses current-driven bulk (CDB) biasing technique to reduce the size of the driver transistors. ...
... Low-swing voltage-mode drivers456 have lower power consumption compare to their current-mode counterparts.Fig. 3 shows a low-swing voltage-mode driver along with its global output driver impedance controller [7]. ...
... Both of the current or voltagemode drivers, shown in Fig. 2, are widely utilized in different serial links. Although current-mode drivers are mostcommonly used [3], the power wasted in the parallel termination led designers to consider low-swing voltage-mode drivers [4][5][6]. This paper focuses on low-swing voltage-mode driver technique and uses current-driven bulk (CDB) biasing technique to reduce the size of the driver transistors. ...
In this paper, a modified structure for low-swing voltage-mode drivers in high-speed serial links is proposed. A dynamic current-driven bulk-biasing technique is applied to the driver transistors to achieve proper channel impedance termination and to minimize the transistors' sizes. Simulation results of an 8-Gb/s serial link in all process corners of a 0.13-μm CMOS technology confirm that, by using the proposed dynamic current-driven bulk-biasing technique, the total size of the driver transistors is reduced by 23%. Moreover, the power overhead of the proposed technique is only less than 0.02% of the total power consumption of the driver.
... A couple of techniques are presented which allow the independent control of the output impedance and preemphasis level. In [9], a voltage-mode driver is implemented with 15 slices and the output impedance is controlled by adjusting the driving gate voltage with an on-chip linear voltage regulator and the pre-emphasis level is controlled by changing the number of slices used for the main-and sub-driver. In [10], the multiple slices of a voltage-mode driver are further divided into binaryweighted sub-units. ...
A 6-Gb/s differential voltage mode driver is presented whose output impedance and pre-emphasis level can be controlled independently. The voltage mode driver consists of five binary-weighted slices each of which has four sub-drivers. The output impedance is controlled by the number of enabled slices while the pre-emphasis level is determined by how many sub-drivers in the enabled slices are driven by post-cursor input. A prototype transmitter with a voltage-mode driver implemented in a 65-nm CMOS logic process consumes 34.8-mW from a 1.2-V power supply and its pre-emphasized output signal shows 165-mVpp,diff and 0.56-UI eye opening at the end of a cable with 10-dB loss at 3-GHz.
... A few lanes of ~1Gbps transmission are sufficient for the amount of content generated on present day mobile devices. These data-rates are modest compared to the multi- Gbps rates achieved in other custom chip-to-chip12 and backplane45 transceivers, but they are also correspondingly cheaper to obtain in terms of area, power and design time. At close to 1Gbps, and for the relatively short interconnect lengths seen on mobile devices, transmit and receive equalization are not required. ...
... On the other hand, a challenge in the design of a serial interface for mobile devices is that the Transmitter (TX) and the receiver (RX) cannot be co-designed -simply because they are made by different manufacturers. Some design choices that are possible in custom transceiver designs12 may not be possible for a TX and RX designed for wide inter-operability. This paper presents a 65nm CMOS 800Mbps voltage mode differential transmitter intended for use in a multi-lane sourcesynchronous link inside a mobile device. ...
... The focus is on achieving low area, low cost, and low design time. In particular we propose a simple slew-rate control scheme that occupies only 0.0027mm 2 area.Fig. 1. shows a typical voltage mode differential transmitter12 terminated with a differential termination R DIFF_RX . The important specifications for the transmitter are the pk-pk voltage swing (V DIFF_pkpk inFig. ...
A slew-rate controlled, 800 Mbps voltage mode differential transmitter is presented here. An add-on, capacitive charge transfer based scheme is used to control output rise/fall times. The transmitter, designed and fabricated in a 65 nm CMOS technology, occupies an active area of 0.02 mm2 and consumes 2.7 mW. Of this, the add-on slew-rate control occupies an area of 0.0027 mm, and consumes 0.5 mW.
... Voltage-mode drivers do consume less current at a lower supply voltage in contrast to current-mode drivers. However they have the difficulty that they requires an additional low-voltage supply for reducing the output voltage swing, since the output voltage swing is constrained by the supply voltage5678. In this paper, we describe a simple but efficient technique to design a voltage-mode driver, which reduces the output voltage swing so that the total drawn current is cut down.Fig. 1 shows the current-mode driver which is usually preferred in transmitters for multi-Gb/s wire-line communication because of the simple design and high-speed capability [3,4]. ...
... They consume less current and introduce ac-coupling without modifying the design, compared to current-mode drivers. InFig. 2 (a), two NMOS transistors act as push and pull resistor [5,6]. NMOS transistors of the driver are operated as resistors since the gate voltage of a driver's NMOS transistor is much higher than the supply voltage of the driver in that configuration. ...
... The driver uses a PMOS transistor as a pull-up resistor since all circuit in the driver block operates with a shared supply, unlike previous voltage-mode drivers which require an additional low-voltage supply. De-emphasis to compensate the inter-symbol-interference due to the narrow bandwidth of the channel is implemented with an auxiliary driver, which have the weak strength and input signals of negative polarity and oneclock latency compared to a main driver [6]. When the input data has a transition, all the PMOS transistor or NMOS transistor is turned on and the driver operates as explained before. ...
At a lower supply voltage, voltage-mode drivers draw less current than current-mode drivers. In this paper, we newly propose a voltage-mode driver with an additional current path that reduces the output voltage swing without the need for compli- cated additional circuitry, compared to conventional voltage-mode drivers. The prototype driver is fabric- cated in a 0.13-μm CMOS technology and used to transmit data streams at the rate of 2.5 Gb/s. De- emphasis is also implemented for the compensation of channel attenuation. With a 1.2-V supply, it dissipates 8.0 mA for a 400-mV output voltage swing.
... A conceptually similar design style has been proposed in series-terminated line drivers [1]–[3] or in the stub-series-terminated logic commonly used in double-data-rate (DDR) memory circuits [4]. Recent work on transmitters with voltage-mode output stages can be found in [5], [6]. Reference [6] also proposes an independent control of the impedance tuning and the equalization, but in contrast to our transmitter that approach is not based on enhancing the sliced output stages with a complete set of de-emphasis weights. ...
... Recent work on transmitters with voltage-mode output stages can be found in [5], [6]. Reference [6] also proposes an independent control of the impedance tuning and the equalization, but in contrast to our transmitter that approach is not based on enhancing the sliced output stages with a complete set of de-emphasis weights. Apart from the high versatility due to the support of many different common mode voltages at the receiver with the same transmitter circuit, the advantages of the SST concept lie in its potential for low-power operation, good technology scaling due to the high content of digital circuitry, and the comparatively large signal swing. ...
A source-series-terminated (SST) transmitter in a 65 nm bulk CMOS technology is presented. The circuit exhibits an eye height greater than 1.0 V for data rates of up to 8.5 Gb/s. A thin-oxide pre-driver stage running at 1.0 V drives 22 parallel connected thick-oxide SST output stages operated at 1.5 V that feature a 5-bit 2-tap FIR filter whose adaptation is independent of the impedance tuning. To achieve a return loss of <-16 dB up to 10 GHz a 40 mum times 40 mum T-coil complements the transmitter output. This half-bit-rate clock SST transmitter has a duty-cycle restoration capability of 5x, and the common-mode voltage noise is below 10 mV rms for high-, mid- and low-level terminations. The chip consumes 96 mW at 8.5 Gb/s and occupies 180 mum times 360 mum. In addition to the transmitter design, guidelines for the T-coil design are presented.
