Fig 3
Context in source publication
Context 1
... from FIFO is read at each clock cycles and is sent to the Cyclic Redundancy Check (CRC) block [9] as well as the state machine of the ethernet MAC transmitter module to perform ethernet packet framing and transmit data serially to the PHY layer. The transmitter module is shown in Figure 2 and the transmitter state machine is shown in Figure 3. The received information on the FPGA physical layer over ethernet by a receive state machine. ...
