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Transmitter Baseband Design modules through external connections. The front-end gen- erates also a digitally adjustable sampling frequency output which is synthesized from the same reference as the inter- nal local oscillator. This output can be externally split if more than one ADC module needs to be fed with an external sampling clock. The RF input interfaces are externally connected to a 4-antenna ULA through high-quality semi- rigid RF cables. The mechanical assembly of the antenna array allows the distance between elements to be adjusted to up to 2 λ at 5.2GHz, and the antenna used is a standard monopole. 2) Algorithm Description: in the DSP section, two processing units, multi-DSP and multi-FPGA, are available for the implementation of complex signal processing algorithms. For the development of the presented demonstrator, all the algorithms were integrated in a Pentek 4292 quad-DSP VME Board. Each of the four TI TMS320C6203 fixed-point DSPs, operating at 300MHz, is in charge of im- plementing the synchronization tasks required for each of the four receive antennas. After parameter estimation and correction, a joint space-time decoding is implemented in a single DSP, as shown in Fig. 3. It is well-known that in SISO WLAN systems, the short preamble has a known periodicity that makes it unique from the synchronization point of view. Due to the cyclic delays applied at the transmitter and depending on the channel response, long training sequences (LTS) may also be endowed with the same periodic characteristics. This is the main source of false alarm in the start of frame (SoF) detection algorithm when a traditional autocorrelation approach is used [6]. The algorithm implemented in this receiver for the frame detection emulates a traditional received signal strength indicator (RSSI) detector in the digital domain. This approach has been shown to be robust to any number of transmit antennas. Once the SoF has been detected, the coarse carrier frequency offset (CFO) is estimated during the short training sequence (STS). The algorithm implemented is based on a classic autocorrelation of the received samples [6] and yields the Maximum Likelihood (ML) estimate of the frequency offset. In the fine CFO estimation, the autocorrelations are applied to the LTS, thereby giving a more accurate estimate. The main goal of the coarse timing estimation algorithm is to detect the starting sample of the first LTS. Based on 

Transmitter Baseband Design modules through external connections. The front-end gen- erates also a digitally adjustable sampling frequency output which is synthesized from the same reference as the inter- nal local oscillator. This output can be externally split if more than one ADC module needs to be fed with an external sampling clock. The RF input interfaces are externally connected to a 4-antenna ULA through high-quality semi- rigid RF cables. The mechanical assembly of the antenna array allows the distance between elements to be adjusted to up to 2 λ at 5.2GHz, and the antenna used is a standard monopole. 2) Algorithm Description: in the DSP section, two processing units, multi-DSP and multi-FPGA, are available for the implementation of complex signal processing algorithms. For the development of the presented demonstrator, all the algorithms were integrated in a Pentek 4292 quad-DSP VME Board. Each of the four TI TMS320C6203 fixed-point DSPs, operating at 300MHz, is in charge of im- plementing the synchronization tasks required for each of the four receive antennas. After parameter estimation and correction, a joint space-time decoding is implemented in a single DSP, as shown in Fig. 3. It is well-known that in SISO WLAN systems, the short preamble has a known periodicity that makes it unique from the synchronization point of view. Due to the cyclic delays applied at the transmitter and depending on the channel response, long training sequences (LTS) may also be endowed with the same periodic characteristics. This is the main source of false alarm in the start of frame (SoF) detection algorithm when a traditional autocorrelation approach is used [6]. The algorithm implemented in this receiver for the frame detection emulates a traditional received signal strength indicator (RSSI) detector in the digital domain. This approach has been shown to be robust to any number of transmit antennas. Once the SoF has been detected, the coarse carrier frequency offset (CFO) is estimated during the short training sequence (STS). The algorithm implemented is based on a classic autocorrelation of the received samples [6] and yields the Maximum Likelihood (ML) estimate of the frequency offset. In the fine CFO estimation, the autocorrelations are applied to the LTS, thereby giving a more accurate estimate. The main goal of the coarse timing estimation algorithm is to detect the starting sample of the first LTS. Based on 

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In this paper, a broadband wireless 4times4 multiple-input multiple-output (MIMO) space-time-block-coded (STBC) OFDM demonstrator is presented. A general description of the hardware architecture of the testbed is shown. The FPGA and DSP-based algorithms implemented at the transmit and receive sides are defined and compared to traditional single-ant...

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... data source consists of a flexible random bit generator. Before the mapping to in-phase and quadrature (I/Q) samples, the output bit stream is cut in frames and a customized signal field is inserted (see Figure 2). No coding or interleaving is applied. ...

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