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A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their ope...
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Context 1
... subthreshold region is a region where the gate- source voltage of a MOSFET is smaller than the threshold voltage of the MOSFET (see [2] for details of the subthresh- old operation of MOSFETs). Figure 4 shows the trans- fer characteristics of nMOS and pMOS transistors (0.35-μm CMOS devices, W/L = 1.5 μm/0.35 μm) we used to design the gate circuit. ...
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Citations
An integer linear programming-based framework to identify the current-mode threshold logic functions is presented. The approach minimizes the transistor count and benefits from a generalized definition of threshold logic functions. It is shown that the threshold logic functions can be implemented in CMOS-based current mode logic with reduced transistor count when the input weights are not restricted to be integers. A novel implementation of rational weights is proposed. Process variations, transistor aging, and circuit parasitics are taken into consideration. Experimental results show that many more functions can be implemented with predetermined hardware overhead, and the hardware requirement of a large percentage of the existing threshold functions is reduced when comparing with the traditional CMOS-based threshold logic implementation.
Current mode is a popular CMOS-based implementation of threshold logic functions, where the gate delay depends on the sensor size. This paper presents a new implementation of current mode threshold functions for improved gate delay and switching energy. An analytical method is also proposed in order to identify quickly the sensor size that minimizes the gate delay. Simulation results on different gates implemented using the optimum sensor size indicate that the proposed current mode implementation method outperforms consistently the existing implementations in delay as well as switching energy.
A new clocked design that uses memristors in current mode logic implementation of threshold logic gates is presented. Memristor based designs have high potential to improve performance and energy over purely CMOS-based current mode logic implementations. The proposed design is clocked, and outperforms a recently proposed combinational method in performance as well as energy consumption. A fault tolerant implementation is analyzed, and it is experimentally verified that scales well in both energy consumption and delay.
A recent approach is capable of identifying threshold logic functions with as many as fifty inputs with small integer weights on the inputs. An analytical method is presented for selecting optimum sensor sizes. This allows us to design large threshold functions with delay much less than a network of CMOS gates. Exhaustive SPICE simulations show that implemented TLGs by the proposed approach consistently exhibit behavior very close to the optimal.
