FIGURE 1 - available via license: Creative Commons Attribution 4.0 International
Content may be subject to copyright.
Source publication
In this paper, a novel method is proposed to build an improved 1-D discrete chaotic map called flipped product chaotic system (FPCS) by multiplying the output of one map with the output of a vertically flipped second map. Two variants, each with nine combinations, are shown with trade-off between computational cost and performance. The chaotic prop...
Contexts in source publication
Context 1
... r is the control parameter and r ∈ [0, 1]. The transfer curve shows the input-output characteristics of a map for different values of the control parameter. The transfer curves for the three seed maps are shown in Fig. 1(a-c) and the transfer curves for their corresponding flipped maps are shown in Fig. 1(d-f). The effect of a control parameter on a dynamical system can be visualized with a bifurcation diagram where for each parameter value, a long sequence of steady-state output values is plotted. The advantage of the bifurcation diagram is that it clearly ...
Context 2
... r is the control parameter and r ∈ [0, 1]. The transfer curve shows the input-output characteristics of a map for different values of the control parameter. The transfer curves for the three seed maps are shown in Fig. 1(a-c) and the transfer curves for their corresponding flipped maps are shown in Fig. 1(d-f). The effect of a control parameter on a dynamical system can be visualized with a bifurcation diagram where for each parameter value, a long sequence of steady-state output values is plotted. The advantage of the bifurcation diagram is that it clearly shows the period doubling process which causes the system to transition from a fixed ...
Context 3
... transfer curves for the nine possible combinations of FPCM are shown in Fig. 4. As we can see from these figures, the output of these FPCMs cover the entire range with more oscillation due to their bimodal characteristics in contrast to the unimodal transfer curve (Fig. 1) of their constituent seed maps which lie at the core of their improved characteristics. Fig. 5 shows the bifurcation diagrams of nine combinations of BFPCS. It shows that the BFPCS has a wider chaotic range with higher signal swing compared to the seed maps when both constituent maps are of the same type, namely ...
Context 4
... transfer curves for the nine possible combinations derived using Table 2 are shown in Fig. 10. As we can see from these figures, unlike BFPCMs, the output of these EFPCMs has a higher signal swing for all parameter values (4 ) which lead to its enhanced performance as demonstrated in the following subsections. ; r ≥ 0.5 T S f (r, x) xn+1 = (1/A) * T (r, xn) * S f (r, xn) A = cf * T (r, xmax) * S f (r, xmax) xmax = 0.5 ; r < ...
Context 5
... Bifurcation diagrams of nine EFPCS. Fig. 11 shows the bifurcation diagrams of nine combinations of EFPCS. These maps have significantly wider (close to 100% in most cases) chaotic range with higher signal swing compared to seed maps( Fig. 2) and BFPCS (Fig. ...
Context 6
... . 12 shows the Lyapunov exponents for all nine combinations using EFPCS. They have positive LE values across almost the entire parameter window and the values are significantly higher compared to their constituent seed maps. These figures also show marked improvement in LE compared to BFCPS (Fig. ...
Context 7
... . 13 shows the comparison of KE value between nine combinations of EFPCS and corresponding seed maps. As (Fig. 7). and BFCPS (Fig. 8 and Fig. ...
Context 8
... numbers between 0 and 1 are divided into 2 64 + 1 states and each value is represented by a 65-bit binary number. The 64 least significant bits (LSB) are used to represent [0,1) and the most significant bit (MSB) is used to include 1. The circuit has two 65-bit inputs r and x. The output is also a 65-bit number denoted by x output as shown in Fig. 16. There are two modules that make up the digital circuit as shown in Fig. 16: 1. Tent_f_Tent: This module implements the mathematical operation needed to compute FPCM. Here, we show results for Tent-flipped-Tent (T T f ) map using both BFPCS or EFPCS scheme. 2. FSM: This module is used to store the value of the state variable x i of the ...
Context 9
... is represented by a 65-bit binary number. The 64 least significant bits (LSB) are used to represent [0,1) and the most significant bit (MSB) is used to include 1. The circuit has two 65-bit inputs r and x. The output is also a 65-bit number denoted by x output as shown in Fig. 16. There are two modules that make up the digital circuit as shown in Fig. 16: 1. Tent_f_Tent: This module implements the mathematical operation needed to compute FPCM. Here, we show results for Tent-flipped-Tent (T T f ) map using both BFPCS or EFPCS scheme. 2. FSM: This module is used to store the value of the state variable x i of the chaotic system as its state. In the first round, the initial state (x 0 ) is ...
Context 10
... have computed the first 60 iterations for T T f map in both MATLAB and FPGA and compared these values in Fig. 17. The sequence produced by MATLAB and FPGA start diverging around 50 th iteration for x 0 = 0.3 and r = 0.5 as shown in figure 17. This is inevitable given the different number representation method between 64-bit IEEE-754 floating-point representation [36] in MATLAB and our fixed point FPGA implementation. However, in security ...
Context 11
... have computed the first 60 iterations for T T f map in both MATLAB and FPGA and compared these values in Fig. 17. The sequence produced by MATLAB and FPGA start diverging around 50 th iteration for x 0 = 0.3 and r = 0.5 as shown in figure 17. This is inevitable given the different number representation method between 64-bit IEEE-754 floating-point representation [36] in MATLAB and our fixed point FPGA implementation. ...
Context 12
... is having a chaotic sequence with good long-term entropic characteristics which can be evaluated by metrics such as LE, KE, and CC. We have calculated these metrics for different values of r for MATLAB and FPGA implementation of T T f using both BFPCS and EFPCS. The comparison results between MATLAB and FPGA for BFPCS and EFPCS are shown in Fig. 18 and Fig. 19, respectively. As it clearly shows, FPGA results match very well with MATLAB results over the entire range demonstrating their functional equivalence. ...
Context 13
... test sequences contain 100,000,032 bits (with a padding of 32 1's at the beginning). FIGURE 21 shows the plots of p-values, organized in ascending order. The linear fits in both plots show close conformity with the generated p-value trends, demonstrating excellent randomness for both BFPCS and EFPCS using T T f based PRNG. ...
Citations
... According to Ross Freeman, one of the founders of Xilinx and the inventor of the FPGA, for many applications, flexibility and customizability are attractive features if implemented properly. When Xilinx launched its third-generation FPGA product, the XC4000 series, in 1991, people began to seriously consider programmable technology [2]. Perhaps since then, the shift to the latest semiconductor processes has been inexorable. ...
This paper designs a simple system that can include electronic clock and stopwatch based on FPGA(Field Programmable Gate Array) and VHDL(Very-High-Speed Integrated Circuit Hardware Description Language). The first chapter briefly introduces the research background. The second chapter introduces the theoretical basis of digital circuits and the hardware and software platform used in this paper. In the third chapter, the design of each sub-module of the system and the overall design of the system are carried out. This chapter is the core chapter of this article, which describes the functions of the module and explains the input and output ports. In this chapter, a core point of digital circuit design is reflected: combining modules that realize simple functions into modules that can realize complex functions. And integrate sub-modules that realize similar functions into a top-level module. The fourth chapter is the logic synthesis of the circuit. The fourth chapter shows the simulation of the core module function and the simulation of the system output. The conclusion section summarizes the interesting parts of the design of this paper.
... Most security applications based on chaotic systems are limited to either softwarebased encryption algorithms [39,53] or hardware implementations, either in a purely digital Field Programmable Gate Array (FPGA) domain [7] or analog circuits using off-theshelf components, such as operational amplifiers or multipliers [54]. Digital or discretecomponent-based analog designs are not suitable for hardware-constrained integrated ...
This paper presents a general method, called “self-parameterization”, for designing one-dimensional (1-D) chaotic maps that provide wider chaotic regions compared to existing 1-D maps. A wide chaotic region is a desirable property, as it helps to provide robust performance by enlarging the design space in many hardware-security applications, including reconfigurable logic and encryption. The proposed self-parameterization scheme uses only one existing chaotic map, referred to as the seed map, and a simple transformation block. The effective control parameter of the seed map is treated as an intermediate variable derived from the input and control parameter of the self-parameterized map, under some constraints, to achieve the desired functionality. The widening of the chaotic region after adding self-parameterization is first demonstrated on three ideal map functions: Logistic; Tent; and Sine. A digitized version of the scheme was developed and realized in a field-programmable gate array (FPGA) implementation. An analog version of the proposed scheme was developed with very low transistor-count analog topologies for hardware-constrained integrated circuit (IC) implementation. The chaotic performance of both digital and analog implementations was evaluated with bifurcation plots and four established chaotic entropy metrics: the Lyapunov Exponent; the Correlation Coefficient; the Correlation Dimension; and Approximate Entropy. An application of the proposed scheme was demonstrated in a random number generator design, and the statistical randomness of the generated sequence was verified with the NIST test.
