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Recent trend researches provide potential results of tunnel field effect transistors (TFETs) for being used in many electronic circuit applications. This work studies the comparative analyses of n+ pocket vertical TFET and dual MOSCAP (D-MOS) vertical TFET to determine their compatibility in RF applications. Synopsys TCAD simulation result shows a...
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This work performs a pragmatic evaluation of the different junctionless devices architectures with channel lengths down to 30 nm on their electrical characteristics. By adopting multiple combinations between the fin height (HFIN) and the fin width (WFIN), chosen from the range of published data in the literature, the devices will operate from doubl...
Negative capacitance (NC) effect in nanowire (NW) and nanosheet (NS) field effect transistors (FETs) provide the much-needed voltage scaling in future technology nodes. Here, we present a comparative analysis on the performance of NC-NWFETs and NC-NSFETs through fully calibrated, three-dimensional computer aided design (TCAD) simulations. In additi...
TCAD Simulations for 30 nm double gate tunnel field effect transistor (DGTFET) reports steeper subthreshold swing, SS ~ 15 mV/dec, ION ~ 10–4 A/µm, and low off-state current IOFF ~ 10−15A/µm as desirable parameters for low voltage applications. The unity gain frequency (fT) increases with Vgs and maximizes at 5.2 × 1011 Hz for Vgs = Vds = 0.7 V. It...
Impacts of source/drain (S/D) recess engineering on the device performance of both the gate-all-around (GAA) nanosheet (NS) field-effect transistor (FET) and FinFET have been comprehensively studied at 5 nm node technology. TCAD simulation results show that the device off-leakage, including subthreshold leakage through the channel (Isub) and punch-...
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... It's important to note that GaAs HEMTs are just one type of technology used for power amplification, and the choice of device depends on the specific requirements of the application, including the desired frequency range, power output, and other performance characteristics. Table 4 compares the device performance with contemporary devices such as GaAs HEMT [35], QuaG GAA MOSFET [12], GME CGT MOSFET [26], Ge/Si TFET [39], and D-MOS VTFET [40] for better perception of device efficiency. The findings derived from this investigation were found to be in perfect agreement with the existing literature. ...
This study focuses on the Electrostatic, linearity, and analogue/RF parameters of a single heterojunction AlGaAs/GaAs-based high electron mobility transistor (HEMT). The device performance for multiple biases has been evaluated using different figures of merit. The Electrostatic, linearity, and analogue/RF performance have been analyzed from the on-wafer DC and RF measurements. A high ON-state current (31.72 mA) and a smaller sub-threshold swing (82.2 mV/dec) have been achieved. Parameters relating to linearities, such as gm, gm2, gm3, VIP2, VIP3, IIP3, 1-dB compression point, IMD3, THD and analogue/RF parameters like TGF, gds, Av, Cgs, Cgd, Cgg, fT and fmax have been analyzed under different Vds, and excellent results have been obtained for all the bias voltages. Higher values of gm, VIP2, VIP3, IIP3, 1-dB compression point, and lower values of gm2, gm3, IMD3, and THD have been obtained. The RF parameters have likewise yielded significant results in a similar manner. The device is revealed to have remarkable linearity and amplifying ability upon investigating the parameters as mentioned above.
... Mathematically given as, The values of VIP2 and VIP3 must be high because the highest point of the VIP2 and VIP3 plots cancel out the second and third-order transconductance coefficients, respectively. 33 The result shows that the proposed AG HJ DL TFET provides maximum amplitude values for the VIP2 and VIP3 values than the SG HJ DL TFET. As a result, we can acquire a more undistorted output signal for the proposed AG HJ DL TFET. ...
Recently, the doping‐less tunnel FET has gained popularity due to its lower process complexity than conventional TFETs with heavily doped source and drain regions. In this literature, we have introduced a symmetric gate Ge/GaAs heterojunction doping‐less TFET(SG HJ DL TFET) using 4.6 eV work function for both the top gate and bottom gate and an asymmetric gate Ge/GaAs heterojunction doping‐less TFET (AG HJ DL TFET) using 3.9 eV work function as top gate and 4.6 eV work function as a bottom gate. A comparative study has been performed between these two devices. The back gate misalignment engineering in the AG HJ DL TFET induces higher charge plasma near the source‐channel junction which will enhance the drain current. Due to a larger drain current, an improved ION/IOFF$$ {\mathrm{I}}_{\mathrm{ON}}/{\mathrm{I}}_{\mathrm{OFF}} $$ ratio (11.8 times), and steeper SS (37%) are achieved in optimized AG HJ DL TFET than SG HJ DL TFET. Furthermore, the Analog/Radio Frequency and linearity performance parameters have been examined, and a significant improvement is noticed in the optimized AG HJ DL TFET. The impact of different interface trap charges (ITCs) on device performances is also investigated and it is found that AG HJ DL TFET shows more immunity to ITCs than SG HJ DL TFET. Finally, the Verilog‐A‐based model has been developed for the AG HJ DL TFET to utilize its circuit‐level behavior. The optimized device‐based Common Source amplifier (CS amplifier) has been simulated in the Cadence Virtuoso tool. The AG HJ DL TFET‐based CS amplifier offers a 6.83% improvement in voltage gain over the other reported work.
... Despite its many benefits, TFET is restrained by its low I ON ambipolar character and random dopant fluctuations (RDFs). 4,5 Many designs utilizing unique materials and structures have been researched in an attempt to improve the overall performance of the TFETs. [6][7][8] Recently, it has also been suggested to replace the doped semiconductor in the source area of a TFET that uses a metal silicide with a comparatively high barrier height. ...
A novel structure of double gate Schottky barrier tunnel field effect transistor (DG-SBTFET) has been designed and simulated. The DG-SBTFET has two sources (NiSi) and two gate metals with an HfO2. Silvaco-TCAD simulator has been used for investigating the analog and radio frequency performance of the DG-SBTFET. The proposed device is compared with the conventional devices in terms of electrical parameters including ION current, ION/IOFF ratio, RF performance including transconductances, cut-off frequency, transit time, gain bandwidth product, transconductance generation factor, and transconductance frequency product. Further, we simulate the linearity characteristics of the DG-SBTFET device is compared it with other conventional devices, including the second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), and third-order input intercept point (IIP3). Hence, the proposed DG-SBTFETis suitable for low-power and high-frequency applications.
... The corresponding mathematical expressions of the aforementioned performance parameters are given below in Eqs. (4)- (14), following the references [22][23][24], ...
In this paper, the impact of vertical channel epilayer thickness (Tepi) of a unique U-TFET has been investigated in the RF domain along with its linearity aspect. Then, a glance has been thrown to the analog domain as well. The entire study has been carried out for the three low-power performance zones. After scrutinizing the linearity vs. analog/RF performance, it has been observed that the most enhanced device in the analog/RF domain is the worst performer with respect to the linearity aspect and vice-versa. This calls for optimization. The 6-nm-Tepi device turns out to be the one. Next, for the first time, a unique process-induced variation study in terms of the deviated Tepi from its optimized value has been introduced to find out the degree of sensitivity of different linearity parameters with respect to the deviation. Intriguingly, no single trend has been observed in terms of the dominance of linearity parameters for the said three zones – the result remains application specific.
... 16 1-dB compression point directly depends on g m1 and inversely depends on g m3. 16,53 An amplifier behaves linearly up to this point, but after that, performance degrades. For improved linearity and lesser intermodulation distortions, a device with a higher 1-dB compression point is preferred, which can be obtained at 0.5 V DS, as shown in Figure 9F. Figure 9G,H shows the variation of distortions HD2 and HD3 with respect to the gate voltage. ...
This article presented a thorough investigation of direct current (DC), analog/radio frequency (RF), and linearity performance of a proposed Ge‐source double gate planner Si‐tunnel field‐effect transistor (TFET) considering different parameter variations using Sentaurus TCAD 2‐D device simulator. The analyses are performed using various quality matrices such as transconductance (gm), total gate capacitance (Cgg), unity gain cut‐off frequency (fT), gain‐bandwidth product (GBP), transconductance frequency product (TFP), etc. It can be perceived that the inclusion of source/channel junction pocket, low bandgap source material, high k gate dielectric, and dual k spacer technology can improve the TFET performances in terms of on‐current (ION), off‐current (IOFF), on–off current ratio (ION/ IOFF) and subthreshold swing (SS) at a supply voltage VDS = 0.7 V. In this article, we used a non‐quasi‐static (NQS) small‐signal model to analyze the behavior of the proposed device in high‐frequency regions. Based on this, the small‐signal admittance parameters were validated up to 1 THz. The proposed TFET produced RF figures of merit (FoM), cut‐off frequency (fT), and maximum oscillation frequency (fmax) in the terahertz range at VDS = VGS = 1 V. Linearity and distortion parameters considered here are VIP2 (interpolated input voltage at which first and second harmonics are equal), VIP3 (interpolated input voltage at which first and third harmonics are similar), IIP3 (third‐order input intercept point), IMD3 (third‐order intermodulation distortion), 1‐dB compression point, HD2 (second‐order harmonic), HD3 (third‐order harmonic) and THD (total harmonic distortion) for different supply voltages. According to the study, the proposed TFET can provide improved RF and linearity performance, ensuring device reliability in low‐power, high‐frequency applications.
The MOSFET faces the major problem of being unable to achieve a subthreshold swing (SS) below 60 mV/dec. As device dimensions continue to reduce and the demand for high switching ratios for low power consumption increases, the TFETs (Tunnel Field Effect Transistors) appears to be a viable device, displaying promising characteristic as an answer to the shortcomings of the traditional MOSFETs. So far, TFET designing has been a task of sacrificing higher ON state currents for low subthreshold swing (and vice versa), and a device that displays both while maintaining structural integrity and operational stability lies in the nascent stages of popular research. This work presents a comprehensive analysis of a heterojunction plasma doped gate-all-around TFET (HPD-GAA-TFET) with a comparison between Mg 2 Si and Si as source material. Charge plasma technique has been employed to induce doping in an intrinsic silicon wafer with the help of suitable electrodes. A low-energy bandgap material, i.e., Magnesium Silicide has been incorporated as source material to form a heterojunction between source and silicon-based channel. A rigorous performance comparison between Si-based GAA-TFET and HPD-GAA-TFET has been drawn with respect to electrical, RF, linearity, and distortion parameters. It is observable that HPD-GAA-TFET outperforms conventional Si-based GAA-TFET presenting an ON-state current (I ON ), SS, threshold voltage (V th ), and current switching ratio as 0.377 mA, 12.660 mV/dec, 0.214 V, and 2.985×10 ¹² ,respectively. Moreover, HPD-GAA-TFET holds faster switching in contrast to Si-based device and is also more reliable. Therefore, HPD-GAA-TFET shows suitable candidature for low-power applications.
This study comprises a simulated assessment of the influence of temperature on transfer characteristics of SiGe source-based Epitaxial layer tunnel field effect transistor (SiGe source ETLTFET). Using the transfer characteristics, the temperature dependence of the RF/analog parameters: transconductance (gm), intrinsic capacitances, cut-off frequency (fT), transconductance generation factor (TGF), transconductance frequency product (TFP), transit time (τ) and minimum noise figure (NFmin) are also presented. Finally, the linearity metrics including higher-order transconductance (gm2 and gm3), input intercept point (IIP3), voltage intercept point (VIP3), intermodulation distortion (IMD3), and 1-dB compression point was evaluated for a wide range of temperature. The findings revealed a substantial impact of temperature on the RF/analog and linearity characteristics. As the temperature rises from 250 to 350 K, the RF/analog characteristics improved, but the linearity figure of merits deteriorates. Moreover, a degraded noise performance (NFmin increases) of the device at elevated temperature was also witnessed.
