(Top left) Core-level Ge(3d) XPS spectra, (top right) core-level N(1s) XPS spectra, and (bottom) relative N atomic concentration from the GeOxNy films as a function of RTN temperature.

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Nanoscale germanium MOS dielectrics - Part II: High-κ gate dielectrics

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Aug 2006

In this paper, atomic layer deposition (ALD) and ultraviolet ozone oxidation (UVO) of zirconium and hafnium oxides are investigated for high-kappa dielectric preparation in Ge MOS devices from the perspectives of thermodynamic stability and electrical characteristics. Prior to performing these deposition processes, various Ge surface preparation sc...

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... physical characterization of the GeO x N y interfacial layers was carried out to inspect their N content and chem- ical stability. X-ray photoemission spectroscopy (XPS) was employed to estimate the N atomic concentration in GeO x N y layers grown on CHF-cleaned Ge at various temperatures for 1 min (Fig. 5). Any surface hydrocarbon layer adsorbed during sample transfer in air was also included in the calculation. The relative ratio of N to the sum of N plus carbon (C) and oxygen (O) increases linearly with the RTN temperature from about 10% to 30%. In addition, the oxidized Ge(3d) peak (Ge n+ ) shifted toward lower binding energy at higher RTN temperatures, which suggests a gradual modification of the Ge bonding configuration. The chemical stability of the GeO x N y layer grown at 600 • C was studied by dipping the sample in either a 20:1 HF solution for 1 min or a DI water for 2 min (Fig. 6). After the N incorporation into GeO x , the resultant GeO x N y layer exhibited a drastic reduction in DI water solubility and an enhanced chemical stability, whereas this stabilized GeO x N y film can easily be etched away in HF solution-the standard SiO 2 ...

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Figure 1. The main atomic percentage change of main components (Si and...

Figure 2. (a)-(c): The oxygen 1s spectra of the interfacial layers from...

Figure 3. (a) Square: Physical thickness of ALD HfO 2 thin films...

Atomic Layer Deposition of High Quality HfO2 Using In-Situ Formed Hydrophilic Oxide as an Interfacial Layer

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Oct 2014

High-quality HfO2 cannot be grown directly on Si substrate using atomic layer deposition (ALD), and an interfacial oxide layer is needed. Traditionally, interfacial oxide layer is formed either in SC1 solution (2 NH4OH: 4 H2O2: 200 H2O) or by ozonated water spraying. A highly hydrophilic SiO2 interfacial layer was in-situ formed in the ALD chamber...

A Steep Slope MBE-Grown Thin p-Ge Channel FETs on Bulk Ge $_{{-on-}}$ Si Using HZO Internal Voltage Amplification

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May 2022
IEEE T ELECTRON DEV

There are vital challenges to harness the unique assets of germanium (Ge) because of Ge-on-insulator (GeOI) processing issues. The advances in molecular beam epitaxy (MBE) technology have enabled the defect-free growth of atomic-level Ge stacks over the standard monolithic silicon platform to leverage the properties of the Ge as a channel layer. Here, we present the first ever report on the authoritative integration of ferroelectric (FE) hafnium zirconium oxide (HZO) over the p-Ge/n-Ge $_{-on-}\text{n}$ -Si system. A rudimentary approach for the carrier modulation in the channel was employed using depletion approximation and negative capacitance (NC) to fabricate HZO and thin p-Ge channel-based FET. The TaN/HZO/TaN stacks were optimized and characterized for enhanced ferroelectricity and non-centrosymmetric orthorhombic phase, which is further confirmed with piezoresponse force microscopic (PFM) analysis. The trivial loop hysteresis conditions to validate the NCFET operation was discussed. The devices demonstrated a lower subthreshold swing (SS) of ~23.44 mV/dec and ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{OFF}}$ ratio of 10 5 . The threshold voltage shift ${V}_{t} = -0.6$ and −1.1 V with the body bias voltage of 0.25 and 0.5 V, respectively. Minimum DIBL measured ~26 mV/V, and rule-out gate induces drain lowering (GIDL) effect due to no gate–drain region overlap.

Impact of Charge Trapping and Constant Voltage Stress on Epitaxial p-Ge-on-p-Si and HfO2 based Al/HfO2/p-Ge-on-p-Si/Al structures

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Mar 2021
IEEE T NANOTECHNOL

The quest for the high speed, low power digital logic circuits urge an imperative demand of compatible high-κ dielectric integration on novel Germanium (Ge) based channel material. Here, first ever a methodical nanoscopic and microscopic probes were attempted to Atomic Layer Deposited, Hafnium Dioxide (HfO 2 ) dielectrics on Molecular Beam Epitaxy (MBE) of p-Ge -on- p-Si stack. Kelvin Probe Force Microscopy based contact potential difference (CPD) analysis reveals that the disintegration of trapped charges lasting for ∼18 hours. The impact of constant voltage stress (CVS) on trapped charges results in variation of threshold voltage (V th ) and hysteresis window (W) were studied. The cyclic Capacitance-Voltage (C-V) characteristics at 0.5 MHz exhibit the shift in the flat band (ΔV fb ), ΔV th , and ΔW at 10V stress were ∼0.84V, ∼0.62V, and ∼0.47V, respectively. While the computed interface trap density (D it ) and total effective charge density (Q eff ) were ∼8.49 × 10 12 eV −1 cm −2 and ∼1.81 × 10 12 cm −2 , respectively. The gate leakage current density, (J) at 5V is 26.53 × 10 −6 A/cm 2 and reduced by a factor of ∼6.8 after 10V, CVS. Whereas the current density (J) increases from ∼26.53 × 10 −6 A/cm 2 at 25 °C by a factor of ∼2 at 125 °C. To study the retention and effect of charge trapping, the stress-time analysis was performed for 8000s at 3V (CVS). The r.m.s. surface roughness of HfO 2 thin films was found to be ∼0.23 nm. X-ray photoelectron spectroscopy (XPS) depth profiling categorized the elemental composition of thin films. These investigations would help to HfO 2 /p-Ge -on- p-Si system interfacial engineering well before the Ge based nano device realization.

Improved Interfacial Properties of HfGdON Gate Dielectric Ge MOS Capacitor by Optimizing Gd Content

Article

Full-text available

Nov 2019
CHINESE PHYS B

High-quality dielectric/Ge interface and low gate leakage current are crucial issues for high-performance nanoscaled Ge-based complementary metal–oxide–semiconductor (CMOS) device. In this paper, the interfacial and electrical properties of high- k HfGdON/LaTaON stacked gate dielectric Ge metal–oxide–semiconductor (MOS) capacitors with different gadolinium (Gd) contents are investigated. Experimental results show that when the controlling Gd content is a suitable value ( e.g. , ∼ 13.16%), excellent device performances can be achieved: low interface-state density (6.93 × 10 ¹¹ cm ⁻² · eV ⁻¹ ), small flatband voltage (0.25 V), good capacitance–voltage behavior, small frequency dispersion, and low gate leakage current (2.29× 10 ⁻⁶ A/cm ² at V g = V fb + 1 V). These could be attributed to the repair of oxygen vacancies, the increase of conduction band offset, and the suppression of germanate and suboxide GeO x at/near the high k /Ge interface by doping suitable Gd into HfON.

Interface states reduction in atomic layer deposited TiN/ZrO 2 /Al 2 O 3 /Ge gate stacks

Article

Mar 2018
JVSTB

In this work, the authors report the application and influence of slot plane antenna plasma oxidation (SPAO) on the quality of Ge/high-k based metal–oxide–semiconductor capacitors. The effect of SPAO exposure on the Ge/high-k interface during atomic layer deposition of the dielectric along with the reliability characteristics has been studied. A significant improvement in the electrical properties has been observed when the high-k stacks are exposed to SPAO treatment. The devices treated with SPAO after Al2O3/ZrO2 deposition (CASE-1) show slightly better equivalent oxide thickness, low leakage current density, and marginally better breakdown characteristics compared to the devices treated with SPAO in-between Al2O3/ZrO2 deposition (CASE-2). This can be attributed to the densification of the gate stack as the plasma exposed to the total stack and the formation of the thick interfacial layer as evident from the X-ray photoelectron spectroscopy (XPS) measurements. A stable and thin interfacial layer formation was observed from XPS data in the samples treated with SPAO in-between high-k stack deposition compared to the samples treated with SPAO after high-k stack deposition. This leads to the low interface state density, low hysteresis, comparable dielectric breakdown, and reliable characteristics in CASE-2 compared to CASE-1. On the other hand, XPS data revealed that the interface is deteriorated in the samples treated with SPAO before high-k stack deposition (CASE-3) and leads to poor electrical properties.

Influence of the atomic layer deposition temperature on the structural and electrical properties of Al/Al 2 O 3 /p-Ge MOS structures

Article

Jan 2018
J VAC SCI TECHNOL A

The influence of deposition temperature on the structural, chemical, and electrical properties of atomic layer deposition (ALD)-Al2O3 thin films is investigated. ALD-Al2O3 films were deposited on p-type Ge substrates at 80, 150, 200, 250, and 300 °C. The atomic force microscopy analysis reveals smooth and cohesive films with extremely low roughness (0.2–0.6) nm at 150, 200, 250, and 300 °C. On the contrary, Al2O3 films deposited at the lowest available deposition temperature (80 °C) exhibit holes and aggregates implying a nonhomogeneous deposition. The x-ray photoelectron spectroscopy (XPS) analysis indicates the presence of stoichiometric Al2O3 films at all deposition temperatures. The calculated thickness from the analysis of XPS spectra seems to be in good agreement with the ALD nominal thickness for the films deposited at all deposition temperatures except the one of 80 °C. Transmission electron microscopy (TEM) analysis reveals a flat interface between Al2O3 and p-Ge in an atomic level. In addition, TEM and XPS analyses indicate the absence of any oxidized interlayer between p-Ge and Al2O3 films. Furthermore, C-V, G-V, C-f, G-f, and J-V measurements were performed in order to study the electrical properties and evaluate the density of interfacial traps (Dit) of the structures prior and following forming gas annealing procedure. Forming gas annealing clearly improves the electrical response of all tested structures, as expected, by reducing significantly the “streching out” effect and the frequency dispersion at the depletion regime. Leakage currents and Dit in the order of 10−4 A/cm² (for applied voltage 1 V) and 10¹¹ eV−1 cm⁻², respectively, were measured-calculated for all tested structures.

Ge(001) surface cleaning methods for device integration

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Full-text available

Jun 2017

In recent years, research on Ge nanodevices has experienced a renaissance, as Ge is being considered a possible high mobility channel material replacement for Si MOSFET devices. However, for reliable high performance devices, an atomically flat and perfectly clean Gesurface is of utmost importance. In this review, the existing methods for cleaning the Ge(001) surface are reviewed and compared for the first time. The review discusses three broad categories of cleaning techniques that have been successfully demonstrated to obtain a clean Gesurface. First, the use of ultraviolet light and/or oxygen plasma is discussed. Both techniques remove carbon contamination from the Gesurface and simultaneously form an oxide passivation layer. Second, in situ ion sputtering in combination with germanium regrowth, which can lead to extremely clean and well-ordered Gesurfaces, is discussed. Finally, various wet-etching recipes are summarized, with focus on hydrofluoric acid (HF), NH4OH, and HCl. Despite the success of HF for Si surface preparation, it is demonstrated that in the case of Ge, HF is outperformed by other chemicals with respect to surface roughness,carbon and oxide removal efficiency. It is shown that several cleaning methods can lead to a perfectly clean Gesurface, but only a few methods can be considered for actual device integration due to their effectiveness, simplicity, and scaling ability.

The impact of ultrathin Al 2 O 3 films on the electrical response of p-Ge/Al 2 O 3 /HfO 2 /Au MOS structures

Article

Full-text available

Aug 2016
J PHYS D APPL PHYS

It is well known that the most critical issue in Ge CMOS technology is the successful growth of high-k gate dielectrics on Ge substrates. The high interface quality of Ge/high-k dielectric is connected with advanced electrical responses of Ge based MOS devices. Following this trend, atomic layer deposition deposited ultrathin Al2O3 and HfO2 films were grown on p-Ge. Al2O3 acts as a passivation layer between p-Ge and high-k HfO2 films. An extensive set of p-Ge/Al2O3/HfO2 structures were fabricated with Al2O3 thickness ranging from 0.5 nm to 1.5 nm and HfO2 thickness varying from 2.0 nm to 3.0 nm. All structures were characterized by x-ray photoelectron spectroscopy (XPS) and AFM. XPS analysis revealed the stoichiometric growth of both films in the absence of Ge sub-oxides between p-Ge and Al2O3 films. AFM analysis revealed the growth of smooth and cohesive films, which exhibited minimal roughness (∼0.2 nm) comparable to that of clean bare p-Ge surfaces. The electrical response of all structures was analyzed by C-V, G-V, C-f, G-f and J-V characteristics, from 80 K to 300 K. It is found that the incorporation of ultrathin Al2O3 passivation layers between p-Ge and HfO2 films leads to superior electrical responses of the structures. All structures exhibit well defined C-V curves with parasitic effects, gradually diminishing and becoming absent below 170 K. D it values were calculated at each temperature, using both Hill-Coleman and Conductance methods. Structures of p-Ge/0.5 nm Al2O3/2.0 nm HfO2/Au, with an equivalent oxide thickness (EOT) equal to 1.3 nm, exhibit D it values as low as ∼7.4 10¹⁰ eV⁻¹ cm⁻². To our knowledge, these values are among the lowest reported. J-V measurements reveal leakage currents in the order of 10⁻¹ A cm⁻², which are comparable to previously published results for structures with the same EOT. A complete mapping of the energy distribution of D its into the energy bandgap of p-Ge, from the valence band towards midgap, is also reported. These promising results contribute to the challenge of switching to high-k dielectrics as gate materials for future high-performance metal-oxide-semiconductor field-effect transistors based on Ge substrates. Making the switch to such devices would allow us toexploit its superior properties.

Growth stress induced tunability of dielectric permittivity in thin films

Article

Jan 2016
J APPL PHYS

Stress is inevitable during thin film growth. It is demonstrated here that the growth stress has a significant effect on the dielectric constant of high-k thin films. ZrO2 thin films were deposited on Ge by reactive direct current sputtering. Stress in these films was measured using in-situ curvature measurement tool. The growth stress was tuned from -2.8 to 0.1 GPa by controlling deposition rate. Dielectric permittivity of ZrO2 depends on temperature, phase, and stress. The correct combination of parameters—phase, texture, and stress—is shown to yield films with an equivalent oxide thickness of 8 A. Growth stresses are shown to affect the dielectric constant both directly by affecting lattice parameter and indirectly through the effect on phase stability of ZrO2.

Interface properties of Al2O3/Ge structures with thin Ge oxide interfacial layer formed by pulsed metal organic chemical vapor deposition

Article

Jul 2014
JPN J APPL PHYS

We have examined the formation of a thin GeO2 layer on a Ge substrate by pulsed metal organic chemical vapor deposition (MOCVD) using tetraethoxygermanium (TEOG) and H2O to precisely control GeO2 layer thickness. Also, we have investigated the feasibility of the use of a thin GeO2 layer formed by pulsed MOCVD at the Al2O3/Ge interface. Pulsed MOCVD enables thin GeO2 layer formation with thickness control by the self-limited adsorption of TEOG. For the growth of a thick GeO2 layer, it is a key to allow TEOG and H2O molecules to sufficiently react. Furthermore, we found that the MOCVD-GeO2 layer has a high etching tolerance to Al2O3 deposition and can reduce the interface state density of the Al2O3/Ge structure. Therefore, GeO2 formation by pulsed MOCVD using TEOG and H2O is a candidate method for realizing high-quality high-k/Ge gate stacks.

Germanium Based Field-Effect Transistors: Challenges and Opportunities

Article

Full-text available

Feb 2014

The performance of strained silicon (Si) as the channel material for today's metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed.

(Top left) Core-level Ge(3d) XPS spectra, (top right) core-level N(1s) XPS spectra, and (bottom) relative N atomic concentration from the GeOxNy films as a function of RTN temperature.

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