Figure - uploaded by Ammar Nayfeh
Content may be subject to copyright.
Top: Cross section high resolution-SEM image (45° cut) (a) no hydrogen anneal; (b) 825 ° C ; Bottom: Topographical AFM image ( 10 μ m × 10 μ m ) of epi-Ge layer; (c) no hydrogen anneal (d) 825 ° C
Source publication
We have studied the effect of hydrogen annealing on the surface roughness of germanium (Ge) layers grown by chemical vapor deposition on silicon using atomic force microscopy and cross-sectional high resolution scanning electron microscopy (HR-SEM). Our results indicate a strong reduction of roughness that approaches 90% at 825 °C. The smoother Ge...
Similar publications
Charge trapping in ultrathin high-k Gd2O3 dielectric leading to appearance of hysteresis in C-V curves is studied by capacitance-voltage, conductance-frequency and current-voltage techniques at different temperatures. It was shown that the large leakage current at a negative gate voltage causes the reversible trapping of the positive charge in the...
Electrical and structural properties of GaSb metal-oxide-semiconductor capacitors with in-situ deposited HfO2 gate dielectric and in-situ deposited amorphous silicon interface passivation layer are presented. Capacitance-voltage characteristics with low C-V stretch out, reduced hysteresis, lower EOT is obtained in a temperature range of 3500C-5500C...
Citations
... However, due to the physical limitations of silicon, it has not been an ideal photonic material for all kinds of on-chip devices including light sources and infrared detectors [7]- [9]. Despite the record-breaking demonstration of active silicon photonic components based on III-V hybrid integrated compounds and germanium [10]- [12]; the fabrication process still requires fabrication techniques to overcome the lattice mismatch with the silicon substrate [13], [14]. Over the past decades, two-dimensional (2D) materials have come to the forefront as viable building blocks of integrated photonic devices [15]- [17]. ...
In-plane optical anisotropy plays a critical role in manipulating light in a wide range of planner photonic devices. In this study, the strong anisotropy of multilayer 2D GeAs is leveraged and utilized to validate the technical feasibility of on-chip light management. A 2D GeAs is stamped into an ultra-compact silicon waveguide four-way crossing optimized for operation in the O-optical band. The measured optical transmission spectra indicated a remarkable discrepancy between the in-plane crystal optical axes with an attenuation ratio of ~ 3.5 (at 1330 nm). Additionally, the effect of GeAs crystal orientation on the electro-optic transmission performance is demonstrated on a straight waveguide. A notable 50 % reduction in responsivity was recorded for devices constructed with cross direction compared to devices with a crystal a-direction parallel to the light polarization. This extraordinary optical anisotropy, combined with a high refractive index ~ 4 of 2D GeAs, opens possibilities for efficient on-chip light manipulation in photonic devices.
... A $100 nm Ge seed layer was grown first at a low temperature of 300 C, and then a $500 nm Ge layer was deposited at 600 C. Subsequently, in situ annealing was carried out under a high vacuum of 10 À6 Pa at 850 C for 1 min with a heating rate of 40 C per minute to improve the crystal quality. 20,21 Subsequently, a $2 lm reverse linearly graded Si x Ge 1-x buffer with x changing from 0 to $0.2 was grown at 630 C, and a $500 nm Si 0.2 Ge 0.8 buffer layer of uniform composition was deposited on top of graded SiGe at the same temperature. For the remaining structures, in order to inhibit the formation of an interfacial transition layer, the chamber was isolated to any gas and pumped to high vacuum after the growth of each layer. ...
An undoped Ge/SiGe quantum well has been grown by ultrahigh vacuum chemical vapor deposition, and the sharp interface with a characteristic length of 0.6 nm is confirmed by cross-sectional transmission electron microscopy and electron energy loss spectroscopy. In addition, a 2D hole gas with a high mobility of up to 4.6 × 10 ⁵ cm ² /V s is achieved in the Hall-bar shaped field effect transistor, showing a low percolation density of 8.7 × 10 ¹⁰ cm ⁻² , a light hole effective mass of 0.071 m 0 , and a high effective g-factor of 11.3. These favorable properties confirm the benefits of high-quality interface, which has promising applications in the field of qubits.
... This buffer layer provides extra nucleation centers for dislocations originating from the big lattice mismatch between Si and Ge. This initial layer effectively assists in decreasing the possibility of 3D island accumulation [39][40][41]. The subsequent growth at high temperatures accelerates the rate of defect motion, which ultimately facilitates annihilation during material growth. ...
In this manuscript, the integration of a strained Ge channel with Si-based FinFETs was investigated. The main focus was the preparation of high-aspect-ratio (AR) fin structures, appropriate etching topography and the growth of germanium (Ge) as a channel material with a highly compressive strain. Two etching methods, the wet etching and in situ HCl dry etching methods, were studied to achieve a better etching topography. In addition, the selective epitaxial growth of Ge material was performed on a patterned substrate using reduced pressure chemical vapor deposition. The results show that a V-shaped structure formed at the bottom of the dummy Si-fins using the wet etching method, which is beneficial to the suppression of dislocations. In addition, compressive strain was introduced to the Ge channel after the Ge selective epitaxial growth, which benefits the pMOS transport characteristics. The pattern dependency of the Ge growth over the patterned wafer was measured, and the solutions for uniform epitaxy are discussed.
... However, due to the physical limitations of silicon, it has not been an ideal photonic material for all kinds of on-chip devices including light sources and infrared detectors [7]- [9]. Despite the record-breaking demonstration of active silicon photonic components based on III-V hybrid integrated compounds and germanium [10]- [12]; the fabrication process still requires fabrication techniques to overcome the lattice mismatch with the silicon substrate [13], [14]. Over the past decades, two-dimensional (2D) materials have This come to the forefront as viable building blocks of integrated photonic devices [15]- [17]. ...
In-plane optical anisotropy plays a critical role in manipulating light in a wide range of planner photonic devices. In this study, the strong anisotropy of multilayer 2D GeAs is leveraged and utilized to validate the technical feasibility of on-chip light management. A 2D GeAs is stamped into an ultra-compact silicon waveguide four-way crossing optimized for operation in the O-optical band. The measured optical transmission spectra indicated a remarkable discrepancy between the in-plane crystal optical axes with an attenuation ratio of ∼ 3.5 (at 1330 nm). Additionally, the effect of GeAs crystal orientation on the electro-optic transmission performance is demonstrated on a straight waveguide. A notable 50 % reduction in responsivity was recorded for devices constructed with cross direction compared to devices with a crystal
a
-direction parallel to the light polarization. This extraordinary optical anisotropy, combined with a high refractive index ∼ 4 of 2D GeAs, opens possibilities for efficient on-chip light manipulation in photonic devices.
... However, the growth of high-quality Ge on Si faces the difficulty of large lattice mismatch and large thermal expansion coefficients between Ge and Si. To decrease the threading dislocation densities (TDDs) and surface roughness of the Ge layers, several methods have been proposed, such as introducing a Ge buffer of low-temperature (LT) and high-temperature (HT) growth [21][22][23][24], As-doped LT-Ge buffer [25], ultra-thin SiGe/Si superlattice buffer layer [26], reversed graded SiGe buffer [27], high-temperature H 2 annealing [28,29], cyclic thermal annealing [30], and selective epitaxial growth (SEG) of Ge buffer [31]. By using the above-mentioned methods, material quality for Ge epilayers has significantly improved. ...
This article presents a novel method to grow a high-quality compressive-strain Ge epilayer on Si using the selective epitaxial growth (SEG) applying the RPCVD technique. The procedures are composed of a global growth of Ge layer on Si followed by a planarization using CMP as initial process steps. The growth parameters of the Ge layer were carefully optimized and after cycle-annealing treatments, the threading dislocation density (TDD) was reduced to 3 × 107 cm−2. As a result of this process, a tensile strain of 0.25% was induced, whereas the RMS value was as low as 0.81 nm. Later, these substrates were covered by an oxide layer and patterned to create trenches for selective epitaxy growth (SEG) of the Ge layer. In these structures, a type of compressive strain was formed in the SEG Ge top layer. The strain amount was −0.34%; meanwhile, the TDD and RMS surface roughness were 2 × 106 cm−2 and 0.68 nm, respectively. HRXRD and TEM results also verified the existence of compressive strain in selectively grown Ge layer. In contrast to the tensile strained Ge layer (globally grown), enhanced PL intensity by a factor of more than 2 is partially due to the improved material quality. The significantly high PL intensity is attributed to the improved crystalline quality of the selectively grown Ge layer. The change in direct bandgap energy of PL was observed, owing to the compressive strain introduced. Hall measurement shows that a selectively grown Ge layer possesses room temperature hole mobility up to 375 cm2/Vs, which is approximately 3 times larger than that of the Ge (132 cm2/Vs). Our work offers fundamental guidance for the growth of high-quality and compressive strain Ge epilayer on Si for future Ge-based optoelectronics integration applications.
... During the first step, the Ge growth follows Stranski-Krastanov mode where a few monolayers of Ge are initially grown, and later nucleation of Ge occurs. The role of LT growth is to promote layer-by-layer growth and to relax the elastic energy in limiting and confining the dislocations without any 3D islanding [26,27]. Then, a high temperature (>500 • C) is employed for the growth of the topmost Ge layer, which offers lower TDD [28]. ...
This work presents the growth of high-quality Ge epilayers on Si (001) substrates using a reduced pressure chemical vapor deposition (RPCVD) chamber. Based on the initial nucleation, a low temperature high temperature (LT-HT) two-step approach, we systematically investigate the nucleation time and surface topography, influence of a LT-Ge buffer layer thickness, a HT-Ge growth temperature, layer thickness, and high temperature thermal treatment on the morphological and crystalline quality of the Ge epilayers. It is also a unique study in the initial growth of Ge epitaxy; the start point of the experiments includes Stranski–Krastanov mode in which the Ge wet layer is initially formed and later the growth is developed to form nuclides. Afterwards, a two-dimensional Ge layer is formed from the coalescing of the nuclides. The evolution of the strain from the beginning stage of the growth up to the full Ge layer has been investigated. Material characterization results show that Ge epilayer with 400 nm LT-Ge buffer layer features at least the root mean square (RMS) value and it’s threading dislocation density (TDD) decreases by a factor of 2. In view of the 400 nm LT-Ge buffer layer, the 1000 nm Ge epilayer with HT-Ge growth temperature of 650 °C showed the best material quality, which is conducive to the merging of the crystals into a connected structure eventually forming a continuous and two-dimensional film. After increasing the thickness of Ge layer from 900 nm to 2000 nm, Ge surface roughness decreased first and then increased slowly (the RMS value for 1400 nm Ge layer was 0.81 nm). Finally, a high-temperature annealing process was carried out and high-quality Ge layer was obtained (TDD=2.78 × 107 cm−2). In addition, room temperature strong photoluminescence (PL) peak intensity and narrow full width at half maximum (11 meV) spectra further confirm the high crystalline quality of the Ge layer manufactured by this optimized process. This work highlights the inducing, increasing, and relaxing of the strain in the Ge buffer and the signature of the defect formation.
... % lays the groundwork to exploit this approach and test its suitability to grow device-quality, thick layers. 20 Future improvements should also include selective-area growth and in situ low temperature thermal cyclic annealing processes, similar to what is currently used for the growth of Ge or SiGe on Si. 21 However, a low thermal budget must be considered to prevent any degradation of GeSn layers, which are inherently metastable. Ex situ treatments such as laser or flashlamp annealing can also be envisaged to reduce dislocation density. ...
(Si)GeSn semiconductors are finally coming of age after a long gestation period. The demonstration of device-quality epi-layers and quantum-engineered heterostructures has meant that tunable all-group IV Si-integrated infrared photonics is now a real possibility. Notwithstanding the recent exciting developments in (Si)GeSn materials and devices, this family of semiconductors is still facing serious limitations that need to be addressed to enable reliable and scalable applications. The main outstanding challenges include the difficulty to grow high-crystalline quality layers and heterostructures at the desired content and lattice strain, preserve the material integrity during growth and throughout device processing steps, and control doping and defect density. Other challenges are related to the lack of optimized device designs and predictive theoretical models to evaluate and simulate the fundamental properties and performance of (Si)GeSn layers and heterostructures. This Perspective highlights key strategies to circumvent these hurdles and hopefully bring this material system to maturity to create far-reaching opportunities for Si-compatible infrared photodetectors, sensors, and emitters for applications in free-space communication, infrared harvesting, biological and chemical sensing, and thermal imaging.
... % lays the groundwork to exploit this approach and test its suitability to grow device-quality, thick layers. 20 Future improvements should also include selective-area growth and in situ low temperature thermal cyclic annealing processes, similar to what is currently used for the growth of Ge or SiGe on Si. 21 However, a low thermal budget must be considered to prevent any degradation of GeSn layers, which are inherently metastable. Ex situ treatments such as laser or flashlamp annealing can also be envisaged to reduce dislocation density. ...
(Si)GeSn semiconductors are finally coming of age after a long gestation period. The demonstration of device quality epi-layers and quantum-engineered heterostructures has meant that tunable all-group IV Si-integrated infrared photonics is now a real possibility. Notwithstanding the recent exciting developments in (Si)GeSn materials and devices, this family of semiconductors is still facing serious limitations that need to be addressed to enable reliable and scalable applications. The main outstanding challenges include the difficulty to grow high crystalline quality layers and heterostructures at the desired Sn content and lattice strain, preserve the material integrity during growth and throughout device processing steps, and control doping and defect density. Other challenges are related to the lack of optimized device designs and predictive theoretical models to evaluate and simulate the fundamental properties and performance of (Si)GeSn layers and heterostructures. This Perspective highlights key strategies to circumvent these hurdles and bring this material system to maturity to create far-reaching new opportunities for Si-compatible infrared photodetectors, sensors, and emitters for applications in free-space communication, infrared harvesting, biological and chemical sensing, and thermal imaging.
... Different alternatives for high-quality Ge films have been explored over the course of years. This includes combined approach, where submicron SiGe buffered layers are used before the two-step growth technique [98,99], direct Ge growth with additional H 2 annealing [100,101], low-energy plasma-enhanced CVD to reduce the overall thermal budget [102], or selective epitaxial growth (SEG) in etched Si recesses [103] (shown in Figure 2). Indeed, SEG is better suited to integrate Ge devices at discrete location in a Si CMOS circuit [104]. ...
Integrated silicon nanophotonics has rapidly established itself as intriguing research field, whose outlets impact numerous facets of daily life. Indeed, nanophotonics has propelled many advances in optoelectronics, information and communication technologies, sensing and energy, to name a few. Silicon nanophotonics aims to deliver compact and high-performance components based on semiconductor chips leveraging mature fabrication routines already developed within the modern microelectronics. However, the silicon indirect bandgap, the centrosymmetric nature of its lattice and its wide transparency window across optical telecommunication wavebands hamper the realization of essential functionalities, including efficient light generation/amplification, fast electro-optical modulation, and reliable photodetection. Germanium, a well-established complement material in silicon chip industry, has a quasi-direct energy band structure in this wavelength domain. Germanium and its alloys are thus the most suitable candidates for active functions, i.e. bringing them to close to the silicon family of nanophotonic devices. Along with recent advances in silicon–germanium-based lasers and modulators, short-wave-infrared receivers are also key photonic chip elements to tackle cost, speed and energy consumption challenges of exponentially growing data traffics within next-generation systems and networks. Herein, we provide a detailed overview on the latest development in nanophotonic receivers based on silicon and germanium, including material processing, integration and diversity of device designs and arrangements. Our Review also emphasizes surging applications in optoelectronics and communications and concludes with challenges and perspectives potentially encountered in the foreseeable future.
... Although many attempts have been made to improve the quality of the epitaxial Ge layer using (a) two-step growth, (b) graded SiGe buffer layer, (c) wafer bonding technology and (d) annealing technologies, it is still difficult to eliminate all the defects generated during epitaxial growth. [54][55][56][57] The first attempt to realize Ge-on-Si waveguides (GOS) was published by Chang et al in 2012. 27 Ge epitaxial layer of 2 μm thickness was grown on a Si substrate by reduced pressure-chemical vapor deposition (RP-CVD) and ∼3 μm wide strip waveguides were patterned by photolithography. ...
While silicon photonic integrated circuits for the near‐infrared (IR) telecommunication band have attracted great research interest in the past decade, recent advances offer opportunities to extend the operational wavelength to the mid‐IR (2.5‐20 μm) for free space communications, sensing, environmental monitoring and much more. In this study, we will comprehensively review the current status of materials available for mid‐IR waveguides and waveguide integrated photodetectors, with a few application oriented examples to illustrate the technological importance and significant growth opportunity for integrated photonics in the mid‐IR regime. However, this wavelength regime also presents new material design and fabrication challenges. Therefore, we will discuss the critical issues prior to commercialization and will briefly summarize the outlook on future research topics along with opportunities.
