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This article discusses the design of an application specific MP-SoC (Multi-Processors System on Chip) architecture dedicated to face tracking algorithm. The proposed algorithm tracks a Region-Of-Interest (ROI) by determining the similarity measures between the reference and the target frames. In our approach, this measure is the estimation of the K...
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... More precisely, our goal is to develop rapid prototyping tools for image processing applications, using parallel homogeneous architecture, as will be described in the next section. In response to that, we have proposed a new MPSoC approach [1] that aims at raising the abstraction level of the specifications for both software and hardware providing the necessary tools supporting the design from the specification down to the embedded implementation. In addition, our methodology proposes a complete generic architecture from which code can be generated automatically. ...
Today, the problem of designing suitable multiprocessor architecture tailored for a target application field raises the need for a fast and efficient multiprocessor system-on-chip (MPSoC) design environment. Additionally, the implementation of image processing applications on MPSoC system will need to exploit the parallelism and the pipelining in algorithms with the hope of delivering significant reduction in execution times. To take advantage of parallelization on homogeneous MPSoCs and to reduce the programming effort, the proposed design methodology offers more opportunities for accelerating the parallelization of sequential processing image algorithms on pipeline architecture. Our approach provides rapid prototyping tool as a graphic programming environment (CubeGen). Further, it offers a set of parallel software skeletons as a communication library, providing a software abstraction to enable quick implementation of complex image processing applications on field-programmable gate array (FPGA) platform. The design of homogeneous network of communicating processor is presented from the hardware and software specification down to synthesizable hardware description. Then, we extend our approach to support more complex applications by implementing a soft multiprocessor for 'multihypotheses model-driven approach for road recognition' and show the impact of various configuration choices (hardware and software) to match the specific application needs. Using the images of a real road scene, the performance results of the road recognition algorithm on a Xilinx Virtex-6 FPGA platform not only achieve the desired latency but also further improve the tracking performance which depends mainly on the number of hypotheses.
... To overcome these requirements, we have proposed new design methodology able to support parallelisation of complete image processing applications using Multiple Instruction Multiple Data architecture with distributed memory (MIMD-DM). In this way, to reduce the overall time to completion, the approach mentioned above is extended by the usage of new design flow [1] in order to increase the abstraction level of the specifications for both software and hardware description. The greatest advantage of our MPSOC approach is the short design time by using a graphical programming environment (called CubeGen). ...
... In our research, we are motivated to develop a new design flow enable describing parallel hardware architecture at a much higher abstraction level than traditional hardware description languages. We focus on Multiple Instruction Multiple Data (MIMD) with distributed memory (DM) parallel architectures which permit diverse communication types (data, task and flow parallelism) [1]. Communication between nodes is realized thanks to the well-known message passing communication model (each node can send and receive message). ...
In this article, we present a new multistage architecture oriented to real-time complex
processing applications. Given a set of rules, this proposed architecture allows the using of
different communication links (point to point link, hardware router…) to connect unlimited
number of parallel computing elements (software processors) to follow the increasing
complexity of algorithms. In particular, this work brings out a parallel implementation of multihypothesis
approach for road recognition application on the proposed Multiprocessor Systemon-Chip
(MP-SoC) architecture. This algorithm is usually the main part of the lane keeping
applications. Experimental results using images of a real road scene are presented. Using a low
cost FPGA-based System-on-Chip, our hardware architecture is able to detect and recognize
the roadsides in a time limit of 60 mSec. Moreover, we demonstrate that our multistage
architecture may be used to achieve good speed-up in solving automotive applications.
Today, the problem of designing suitable multiprocessor architecture tailored for a target Neural Networks applications raises the need for a fast and efficient MP-SOC (MultiProcessor System-on-Chip) design environment. Additionally, the implementation of such applications on multiprocessor designs will need to exploit the parallelism and pipelining in algorithms with the hope of delivering significant reduction in execution times. To take advantage of parallelization on homogeneous multiprocessor architecture and to reduce the programming effort, we provide new MP-SOC design methodology which offers more opportunities for accelerating the parallelization of Neural Networks algorithms. The efficiency of this approach is tested on many examples of applications. This work is devoted to the design and implementation of a complete intelligent controller parking system of autonomous mobile robot based on Multi-Layer Feed-Forward Neural Networks. To emphasize some specific requirements to be considered when implementing such algorithm, we propose new parallel pipelined architecture composed of several computational stages. Additionally, we especially suggest a parallel software skeleton “SCComCM” aimed at being employed by the developed multistage architecture. The experimental results show that the proposed parallel architecture has better speed-up, less communication time, and better space reduction factor than the hand tuned hardware design.
