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This study aims for a new 11T static random access memory (SRAM) cell that uses power gating transistors and transmission gate for low leakage and reliable write operation. The proposed cell has a separate read and write path which successfully improves read and write abilities. Furthermore, it solves the row half select disturbance and utilises a...
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Citations
... Because of its unsatisfactory RSNM (read static noise margin) at low V DD , the conventional 6T SRAM has a significant probability of reading disturbance. As a result of its failure to maintain the device strength ratio under minimum energy operation, the cell cannot be able to switch the storage node data, resulting in writing failure (Lorenzo and Pailly 2020). To solve the issues in SRAM cells, numerous design configurations have been developed so far. ...
This paper investigates a low leakage power 8 T (LP8T) SRAM cell with high read and write stability. The proposed LP8T (PLP8T) SRAM cell has separate write and read bit lines. As an outcome, the read disturbance is removed. Furthermore, the utilization of a schmitt-trigger (ST) inverter enhances the read stability. Moreover, the write assist technique can enhance the writing ability. When compared to conventional-6 T SRAM, the PLP8T SRAM cell improves HSNM, RSNM, and WSNM by 1.4× 2.3 × and 1.3× respectively. The PLP8T SRAM's read and write access times are lowered by 53.24 and 42.18%, respectively. The PLP8T SRAM has a 50% lower read and write power than conventional-6 T SRAM. In addition, there will be a sufficient improvement when compared to chang10T, HSWA9T, SEDFC8TT, and ST11T SRAM cells.
... On an average 40-50 % of dynamic power in any smart internet of things (IoT) based system is consumed by SRAM memory devices [2,9,[80][81][82][83]. Several research efforts focusing on developments of SRAM cells and memories have been put forth by the researchers in the past [10][11][12][13][14][15]. Techniques like multi-threshold transistors [16], multiple-supply voltage [17], multiple-voltage logic representation [18], power gating [12], clock-gating [19], feedback loop cutting [11,14], decoupled read circuit [13,15], have been introduced by researchers to improve the performance of SRAM cells. ...
... Several research efforts focusing on developments of SRAM cells and memories have been put forth by the researchers in the past [10][11][12][13][14][15]. Techniques like multi-threshold transistors [16], multiple-supply voltage [17], multiple-voltage logic representation [18], power gating [12], clock-gating [19], feedback loop cutting [11,14], decoupled read circuit [13,15], have been introduced by researchers to improve the performance of SRAM cells. However, the performance of traditional CMOS technology-based SRAM cells is limited by short channel effects (SCEs) accompanying with scaled technology nodes [20][21][22][87][88][89][90][91]. ...
... However, a write-assist mechanism is necessary to prevent write failure. The 11T SRAM cell suggested in [24] employs write assist feedback cutting mechanism to enhance WSNM, but due to its three serial connected transistors in its read route, it exhibits a larger read delay. Additionally, it has a slow writing performance because, during the write operation, one of the inverters' feedback lines was disconnected, converting the cell core of this cell into two inverters with cascade connection. ...
Many scientists are working to develop a static random-access memory (SRAM) cell that used little power and has good stability and speed. This work introduces a fin field effect transistor developed SRAM cell with 10 transistors (10T FinFET SRAM). A cross connected standard inverter and schmitt-trigger inverter is used in the proposed 10T FinFET SRAM cell. We introduce the schmitt trigger based SRAM cell with single-ended read decoupled and feedback-cutting approaches to enhance the static noise margin (SNM) and access time of the SRAM cell. The proposed cell’s power utilization is decreased with the help of stacked N-FinFETs. For determining the relative performance of the proposed 10T FinFET SRAM cell design in terms of fundamental design metrics, it has also been compared with some of the current SRAM cells, including 6T, SBL9T SRAM, 10T SRAM, and DS10T SRAM. The simulation results at 0.6V demonstrate that the suggested design achieves low power utilization when Reading, writing and hold modes of operation in comparison to the aforementioned bit cells. It maintains a high SNM during all operations. The suggested cell is the one with fastest read access. The simulation is carried out with cadence tool using FinFET 18nm technology.
... It has also been forecasted by researchers that process variation may limit the required minimum voltage for read and write operations [18,24]. Researchers have proposed several SRAM topologies with improved outcomes when compared to traditional topologies [11][12][13][14][15]. ...
The need for power-efficient devices, such as smart sensor nodes, mobile devices, and portable digital gadgets, is markedly increasing and these devices are becoming commonly used in daily life. These devices continue to demand an energy-efficient cache memory designed on Static Random-Access Memory (SRAM) with enhanced speed, performance, and stability to perform on-chip data processing and faster computations. This paper presents an energy-efficient and variability-resilient 11T (E2VR11T) SRAM cell, which is designed with a novel Data-Aware Read–Write Assist (DARWA) technique. The E2VR11T cell comprises 11 transistors and operates with single-ended read and dynamic differential write circuits. The simulated results in a 45 nm CMOS technology exhibit 71.63% and 58.77% lower read energy than ST9T and LP10T and lower write energies of 28.25% and 51.79% against S8T and LP10T cells, respectively. The leakage power is reduced by 56.32% and 40.90% compared to ST9T and LP10T cells. The read static noise margin (RSNM) is improved by 1.94× and 0.18×, while the write noise margin (WNM) is improved by 19.57% and 8.70% against C6T and S8T cells. The variability investigation using the Monte Carlo simulation on 5000 samples highly validates the robustness and variability resilience of the proposed cell. The improved overall performance of the proposed E2VR11T cell makes it suitable for low-power applications.
... The memory cells another major performance metric is access time. Access time is defined as maximum time required to read or write the data in the memory cell [17]. Read access time is defined as the time difference between the wordline reaches half of the VDD to minimum 50mV voltage difference developed between the both bitlines [18]. ...
... The most trivial method to lower power consumption is to lower the operational V DD for the cell [5]. But this is limited by the variations caused by processvoltage-temperature (PVT) in the nanometer vicinity [6]. Also, the declining trends for V DD have resulted in standby power dominating dynamic power [7]. ...
Cache memory is a key component for most microprocessors in embedded system. The increasing processing load has resulted in an upsurge in the demand for low power, high performance SRAM bit cells. Consequently, in this paper a 7T bit cell is designed for feature size 32 nm and 300 mV supply voltage. The improvement in the performance of the proposed cell is validated against the results obtained for pre-existing 6T, 7T, 8T, 9T, and 10T cells. The read and hold noise margin for the cell is obtained to be 96 and 68 mV respectively, whereas the static margin for the write operation is 170 mV. To perform a successful write operation, a pulse-width of 30 ns is utilized. The power analysis reveals that the proposed cell has minimal read/write power consumption. The leakage power for the cell is 8.4 pW and 1.2 pW for Q = ‘0’ and ‘1’ respectively. Tolerance analysis justifies that the cell maintains its functionality and yields credible outputs under process-voltage-temperature variations for static performance metrics. The layout for the proposed 7T cell occupies 0.584 µm² area. This is 5.55% smaller than a single ended 6T. The area for other 7T counterparts, 8T, 9T, and 10T cells is larger than the proposed cell.
... The use of static random access memories (SRAMs) is continuously increasing in system-on-chips (SoCs) designs to improve the logic performance [1]. The demand for portable applications such as mobile phones, laptops, and medical equipment, and battery-operated devices like internet-ofthings (IoTs) and wireless sensor networks (WSNs) require low-power consumption in the SoCs [2]. Hence, the design of low-power SRAMs is the priority. ...
... Although an SRAM cell can dissipate lower power in the near-/subthreshold region (where the V DD is slightly higher/lower than the threshold voltage (V th ) of the transistor), it must face the increasing manufacturing process, voltage, and temperature (PVT) variations, reduced cell stability, degraded voltage margin, and prevailing leakage current in this region [4,5]. In the advanced technology nodes coupled with V DD reduction, the random dopant fluctuations (RDF) increase the V th variations and lead to on-chip SRAM malfunctioning during the read and write operations because there is an exponentional relationship between SRAM static noise margin (SNM) and V th in the sub-V th region [2,5]. Furthremore, in the scaled technology nodes, SRAM cells become susceptible to soft-errors. ...
... There is, thus, the need for developing circuit-level techniques to overcome these issues. The most common approaches available in the literature are: readdecoupling technique, feedback-cutting technique [14][15][16][17][18][19][20], power-gating technique [2,[21][22][23], floating the cell V SS [24,25], single-ended operations [22,[26][27][28], Schmitt-trigger (ST)-based SRAM design [3, 15, 17-19, 22, 28-30], stacking of transistors [31], bit-interleaving [14,16,19,20,29,32], negative bitline [26,33], wordline boosting [33][34][35]. The well-known technique for RSNM improvement is the read-decoupling, in which the bitlines is fully decoupled from the internal storage nodes of the cell during the read operation. ...
Portable applications and battery-operated devices require highly reliable, stable, and low-power nanometer-sized embedded cache static random access memory (SRAM) cells. The conventional 6-transistor (6T) SRAM cell and its variants suffer from malfunctioning during the read/write operations, and instability, and are vulnerable to the multi-bit soft-error rate at scaled technology node and low supply voltage (VDD). In this regard, this paper proposes an 12T SRAM cell with reliable functioning and reduced multi-bit soft-errors appropriate for low-power portable applications. This cell performs single-end bitline decoupled read operation and write data-dependent feedback-cutting-aware differential write operation to improve the read static noise margin (RSNM) and write static noise margin (WSNM), respectively. The presence of stack transistors in the cell core and read path, and also high virtual ground (VGND) minimize the leakage power dissipation. The proposed cell is compared with other state-of-the-art SRAM cells at VDD=0.7 V and under harsh process, voltage, and temperature (PVT) variations. It offers at least 1.18X higher RSNM, 1.27X higher WSNM, and 2.02X lower leakage power dissipation. It also shows the second-best read power and incurs a penalty in write power. This cell shows at least 1.17X, 1.32X, and 1.04X smaller spread in read delay, RSNM, and WSNM, respectively, when subjected to PVT variations. In addition, the proposed cell eliminates the write half-select disturbance by employing a separate gate to drive the access transistors and thus column-interleaving structure and error correction coding can be applied to reduce multiple-bit upset and increase soft error immunity. The soft-error in the proposed cell is reduced by at least 1.37X in critical charge. Generally, the proposed cell offers the best overall performance among all the compared cells by showing the highest proposed figure of merit.
... This SNM is calculated in the memory cell's read, write, and hold operations. Read SNM (RSNM) and write SNM(WSNM) depending on the cell ratio (CR) and pull-up ratio (PR) [25], [26]. For a fair comparison, we use nominal values for all the designs. ...
... Various configurations of SRAM cells have been proposed in the literature over the years to achieve better performance than conventional design. SRAM cells proposed in [17,22,27] utilize the read decoupling technique to isolate the data storing nodes from the reading access path during the read operation to overcome conflicting read/write requirements induced by the conventional 6T SRAM cell. This technique improves the cell's RSNM to be as high as hold SNM (HSNM). ...
... Various SRAM cells have been presented in the literature [2,6,22,27] to achieve the low-power operation. This is due to the application of single bitline to reduce the switching activity factor of the bitline (α bitline ) to less than half during the read/write operation. ...
... To solve this problem, a feedback-cutting NMOS transistor or transmission gate is inserted inside the cell core of the SRAM cells proposed in [2,10,27] to remove the feedback path of the cross-coupled inverters pair during the write operation, resulting in WSNM improvement. The single-bitline 11T SRAM cell projected in [22] employs power-gated transistors to cut the power rails off from the data storing node Q or QB during the write operation to improve the WSNM. Furthermore, the connection of several access transistors to the same bitline increases overall bitline capacitance, and therefore, the 11T cell [22] shows longer read delay and higher dynamic power. ...
This paper investigates a novel highly stable and robust single-ended 10T SRAM cell appropriate for low-power portable applications. The cell core of the proposed design is a combination of a normal inverter with a stacked NMOS transistor and a Schmitt-trigger (ST) inverter with a double-length pull-up transistor. This improves hold stability and leakage power dissipation. The read and write operations of the proposed cell are performed with the aid of separated paths and bitlines, lowering power consumption. The strong cell core and decoupled read path eliminate the read-disturbance issue in the proposed cell, resulting in read static noise margin (RSNM) enhancement. Furthermore, the feedback-cutting write-assist technique used in the proposed design mitigates the writing ‘1’ issue; consequently, write static noise margin (WSNM)/write margin (WM) improves. To prove the superiority of the proposed SRAM cell in various performance metrics, it is compared with state-of-the-art SRAM cells, introduced as 6T, TG9T, 10T-P1, and SB11T, using HSPICE and 16-nm CMOS technology node taking into consideration the impact of the severe process, voltage, and temperature (PVT) variations. Obtained results at VDD = 0.7 V show that the proposed design offers the highest HSNM/RSNM/WSNM (or WM). The read/write delay of the proposed cell is 3.92X/2.37X higher than that of the 6T SRAM cell due to its single-ended reading/writing structure. However, in terms of power consumption, the proposed cell exhibits 1.64X/1.54X lower than that of 6T SRAM cell. Though the proposed cell occupies a 1.24X higher area compared with the 6T SRAM cell due to its higher count of transistor, it shows the highest proposed figure of merit among all the studied SRAM cells, which is 26.90X higher than that of 6T SRAM cell.
... Another single-end cut-off propagation type is SRAM-11T cell. 43 As shown in Figure 12, the transmission gate type of transistors is considered for bit line control, and a pass transistor is used between the bit line data to one of the inverter inputs. Usage of pass transistors reduces the feedback path between the back and back inverters. ...
... The designs count is shown in the pie chart Figure 13. 43 Among the 24 designs, 12T latch, 44 DICE-12T, 45 Quatro-10T, 46 WE-Quatro-12T, 47 NS,PS-10T, 48 RHBD-12T, 49 RHBD-10T, 50 Nwise-10T, 51 QUCCE-10T,12T, 52 RHMP-12T, 53 and RHMN-12T 54 are partially immune to SEU. ...
Over the past four decades, single event upset (SEU) and single event multiple node upset (SEMNU) have become the major issues in the memory area. Moreover, these upsets are prone to reliability issues in space, terrestrial, military, and medical applications. This article concisely reviews different researchers and academicians who proposed resilience techniques and methods to mitigate this upset mess. In addition, we also investigated the importance of critical charge and the impact of critical charge on device scaling parameters in upset mechanism, probability of memory failure, and the figure of metrics for the stability of memory cells.
