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Timing Chart: An Example
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This paper addresses the specification and verification of hardware interface behaviors using an algebra of communicating timing charts (ACTC for short) whose underlying user model is the well known timing diagram. Terms modeling hierarchical timing charts are built in two steps. First, basic terms corresponding to the leaf charts are built, and th...
Contexts in source publication
Context 1
... charts can be formed using a number of composition operators. As an Example, Figure 1 depicts a leaf timing chart specifying an interface behavior*. The chart is defined over four ports: CS, RE and ADDR (input ports), and DATA (output port). ...
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... cons: Chart states "The example is inspired by the read cycle of the NSI00415 memory (NS Corp. ) that Chart must execute its events at the time instants that validate the condition cons which consists of a system of linear inequalities. The reactive constructs define the reaction of an action within a time interval w.r.t.* a set of actions: e.g., in the example of Figure 1 if we assume that the timing chart without the reactive constraints is represented by the term Chart then Latest(do,{ro,avo},[m,Mj,Chart) describes the fact that the event do will be executed within the interval [m, Mj after the execution of the last event in {ro, avo}. Restriction can be used to describe the timing assumptions about the environment under which the system described by means of the reactive constructs operates. ...
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... 1 The ACTC{3 specification of the timing chart depicted in Figure 1 is given by the expression Read ( Figure 2). As we shall see in Section 4, the order in which we apply the assumption and the reactive constructs has no effect on the behavior of a term. ...
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... in practice this parameter in leaf charts is small. Figure 1, the reactivity procedure starts exploring from the root node represented by its ACTC intermediate form (Example 2). A finite partition of its rooted graph is built as follows: Since only cSo can be executed first, the root node has one possible deadlock-free successor n1. ...
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... the example, all the enumerated nodes are deadlock-free. Thus, the chart of Figure 1 is well-reactive. ...
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Citations
... In this paper, we describe a relative scheduling method for specifications inspired by timing diagrams as formalized in [14,15,19,21]. In summary, the main distinguishing charactersitics of our approach are as follows: ...
... All diagrams can also be annotated by VHDL procedures, variables, and predicates. For a useful subset of this specification language we have defined the formal semantics and provided axiomatization [19], including conversion to a normal form that can be used to transform the specification to a network of Timed Automata for verification using existing tools. Furthermore, the verification of causality and compatibility on leaf-level diagrams can be efficiently carried out using Constraint Logic Programming based on Relational Interval Arithmetic [20,21]. ...
We introduce a new method for scheduling under real-time constraints that is suitable for synchronous system implementations. The input specification is in the form of timing diagrams in which the occurrence times of signal transitions or actions are related by linear constraints, expressing the assumptions on the input actions (the environment) and the commitments on the output actions. Provided that the specification is causal, we give an algorithm for deriving ASAP and ALAP relative schedules for the output actions. We then present a new algorithm for determining whether a given clock period is correct. Based on a schedule and a valid clock period, we transform the specification into a discrete- time relative schedule. Such a schedule serves as the basis for implementing a synchronous state-machine controller.
