Time delay estimation block diagram. 

Time delay estimation block diagram. 

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Low frequency communication, taking advantage of the features of low frequency electromagnetic signals in near field, is widely used in through-the-earth (TTE) wireless applications. However, the low frequency non-Gaussian noise severely limits the communication performance. In this paper, an adaptive noise cancellation algorithm based on time dela...

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... shown in Figure 3, the proposed algorithm includes three modules: time delay estimation module, delay and channel control module, and noise cancellation module. As shown in Equation (17), there are (2P + 1) multiply-accumulate operations and one exponential operation for each sample to get the time delay estimation value. In order to obtain high time delay estimation accuracy, all the operations should be executed in one sampling period and the sampling period should be reduced [31]. Therefore, acceleration of computing is needed. FPGA is more suitable for multiple-instruction, single-data (MISD) applications when power and space considerations outweigh price [32]. In order to execute the proposed algorithm in real time, the proposed algorithm is implemented on FPGA. In this paper, the sampling frequency is 1 MHz and the ADC is 14 bit. Next, this system is described in detail. Figure 4 shows the time delay estimation block diagram. For each channel, the noise signal x (k) is stored in register stack and P is set to be 32. Through the multiply-accumulate (MAC) operation, the noise signal x (k) is multiplied by sinc and f (v) functions. To reduce the computational complexity, the sinc and f (v) functions are stored in two lookup tables. The values of sinc and f (v) functions are obtained from the lookup tables, based on the time delay estimation value D (k) from previous iteration. Then the time delay estimation value is updated based on Equation (17). After getting the time delay values of all channels, the values are processed by the delay control module, which is shown in Figure 5. In order to reduce the computational complexity, we use mean absolute error (MAE) of D (k) rather than the variance to evaluate the correlation between the primary input and the reference inputs. Then the reference input with least MAE will be selected as the reference noise. We will also obtain the time delay value D c (k) inserted in the primary ...