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Three typical implementations for static latch. 1) SR latch similar to SRAM cell with special transistor sizing. 2) D latch based on SR NAND latch. 3) D latch by pass transistor logic. Our technique is applicable to all cases. III. STRUCTURES OF JLATCH AND JFF
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![Fig. 2: A robust SRAM cell [2] implemented by combining four SRAM cells...](profile/Ihsen-Alouani-2/publication/317353639/figure/fig6/AS:667033427537921@1536044570412/A-robust-SRAM-cell-2-implemented-by-combining-four-SRAM-cells-like-a-ring-bit-lines_Q320.jpg)
In this paper, we propose Joint Latch (JLatch) and Joint Flip-Flop (JFF), two novel reconfigurable structures which bring the reconfigurability of reliability to user latches and flip-flops (FFs) in reconfigurable devices such as FPGAs. Specifically, we implement two reconfigurable storage elements that exploit a trade-off between reliability and a...
Contexts in source publication
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... access circuitry and transistor sizing in some implementations are quite differ- ent than SRAM cell. Three typical latch implementations are shown in Figure 3. To store a value into a latch, in (1), the value is pushed inside which requires proper transistor sizing, similar to SRAM cell. ...
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... in (2) and (3), to write a new value, the feedback loop is broken by setting the enable input. JLatch technique is applicable to all cases in Figure 3. ...
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... of the pull-up or pull-down transistors has to be at least two times stronger than the other. The latch (1) in Figure 3 has already such necessary sizing, but for other two, size of transistors inside data retention feedback loop should be adjusted accordingly. In the cases that latch/FF's biased output voltage is not acceptable, output buffers which are used in many practical designs can solve the issue. ...
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... after disappearance of fault source, faulty bits are recovered instantly. In the first latch in Figure 3, which is similar to standard SRAM cell, sizing is already biased where'0' is stronger than '1'. But in most of latch/FF implementations such as the second and third ones in Figure 3, transistor sizings are as normal CMOS gates and not similar to SRAM cell. ...
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... the first latch in Figure 3, which is similar to standard SRAM cell, sizing is already biased where'0' is stronger than '1'. But in most of latch/FF implementations such as the second and third ones in Figure 3, transistor sizings are as normal CMOS gates and not similar to SRAM cell. Hence, the JLatch technique is not directly applicable to these, unless sizing of their pull-up and pull-down networks are adjusted properly. ...
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... simulated our technique on Advanced Design System (ADS) with 22nm predictive technology model library [14]. Transistor sizes for all latches of Figure 3 are selected as follows: ...
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... are performed for three latches in Figure 3 and their hardened versions while they are in hold state. In Figure 9, the achieved improvements have been depicted. ...
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... SER by cell decreases exponentially with Q crit and then, according to Q crit values shown in Table I, the joint latch has a SER that is practically equals to zero, which implies its full immunity against particle strikes. K is a proportionality constant, φ is the neutron flux with energy greater than 1MeV, A is the sensitive area of the Fig. 9: Improvement achieved by hardening latch implementa- tions of Figure 3. The y-axis is maximum tolerable amplitude of injected current pulse, for every pulse width on x-axis. ...
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... the delay of voter is not added to critical path like conventional majority voters. In Figure 10, the delay of normal DFF, TMR DFF, and JDFF (as was shown in Figure 5) with implementation of latch 3 (as was shown in Figure 3) are compared for V dd ranging from 0.5V to 0.9V. Delay is measured as the time between clock edge and the time in which output signal reaches V dd /2 while a minimum size inverter is at output as load. ...
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... In the hold state, a single event may upset the state of the latch or FF, and these erroneous values are not corrected until a correct value is written into the latch or flip-flop. There are broad spectrums of SEU mitigation techniques proposed in recent years [3][4][5][6][7][8][9][10][11][12][13][14]. Recently proposed radiation-hardened designs include triple modular redundancy (TMR), dual interlocked cell (DICE) and Quatro cell and so on, are the most popular techniques to mitigate SEUs in memory cells such as D-FF. ...
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