Figure - available from: International Journal of Reconfigurable Computing
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This XOR memory has 3 ports. B i n and B o u t are part of the same port. Port B controls the address of each BRAM’s read port in B c o l u m n and each BRAM’s write port in B r o w . Writing to memory using port B requires reading from BRAMs in B c o l u m n (except the one in B r o w ) as well as writing to the BRAMs in B r o w . Reading from memory requires reading from all the BRAMs in B c o l u m n . Because the same read port on the BRAMs is used for reading and writing to the memory, it is not possible to split port B into a read-only port and a write-only port as it is with LVT.
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On-chip multiport memory cores are crucial primitives for many modern high-performance reconfigurable architectures and multicore systems. Previous approaches for scaling memory cores come at the cost of operating frequency, communication overhead, and logic resources without increasing the storage capacity of the memory. In this paper, we present...
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Citations
... The reason is that the resource provides by the FPGA's are inefficient to use multi-ported memories. There are many approaches available in the existing survey to implement the multi-ported memory modules like adaptive logic modules (ALM) based, Replication based, multi-pumping based, line value table (LVT), and banking based approach's [3]- [5]. The multi-ported memory controller (MPMC) is used to transfer a large amount of data by providing storage resource sharing on time. ...
span lang="EN-US">The multiple read and write operations are performed simultaneously by multi-ported memories and are used in advanced digital design applications on reprogrammable field-programmable gate arrays (FPGAs) to achieve higher bandwidth. The Memory modules are configured by block RAM (BRAMs), which utilizes more area and power on FPGA. In this manuscript, the techniques to increase the read ports for multi-ported memory modules are designed using the bank division with XOR (BDX) approach. The read port techniques like two read-one write (2R1W) memory, hybrid mode approach either 2R1W or 4R memory, and hierarchical BDX (HBDX) Approach using 2R1W/4R memory are designed on FPGA platform. The Proposed work utilizes only slices and look-up table (LUT's) rather than BRAMs while designing the memory modules on FPGA, which reduces the computational complexity and improves the system performance. The experimental results are analyzed on Artix-7 FPGA. The performance parameters like slices, LUT utilization, maximum frequency (Fmax), and hardware efficiency are analyzed by concerning different memory depths. The 4R1W memory design using the HBDX approach utilizes 4% slices and works at 449.697 MHz operating frequency on Artix-7 FPGA. The proposed work provides a better platform to choose the proper read port technique to design an efficient modular multiport memory architecture.</span
... Multi-port RAMs have been designed before, but none achieve our desired performance. This work was first presented inTownsend et al. (2015a). ...
The multi-ported memories (MPMs) are essential and are part of the parallel computing system for high-performance features. The MPMs are commonly used in most processors and advanced system-on-chip (SoC) for faster computation and high-speed processing. In this manuscript, efficient MPMs are designed using the integration of hierarchical bank division with xor (HBDX) and bank division with remap table (BDRT) approaches. The BDRT approach is configured using remap table with a hash write controlling mechanism to avoid write conflicts. The different multiple read ports are designed using BDX, and HBDX approaches are discussed in detail. The results of 2W4R and 3W4R memory modules are analyzed in detail concerning chip area, operating frequency (MHz), block random access memories (BRAMs), and throughput (Gbps) for different memory depths on virtex-7 field programmable gate array (FPGA). The 2W4R utilizes 2.27% slices, operates at 268 MHz frequency by consuming 64 BRAMs for 16K memory depth. Similarly, the 3W4R uses 2.28% slices, operates at 250 MHz frequency by consuming 96 BRAMs for 16K Memory depth. The proposed designs are compared with existing MPM approaches with better chip utilization (Slices), frequency, and BRAMs on the same FPGA device.
Most of the FPGAs support dual-port RAMs, and it is challenging to implement MPM on FPGA. In this manuscript, the MPM module using Live Value Table (LVT) and XOR approaches are designed to improve the performance metrics. The 2W4R and 3W4R examples are considered to create the MPM using LVT, and XOR approaches. The MPM (2W4R and 3W4R) modules are synthesized on Virtex-7 FPGA and discuss the performance parameters like chip area (Slices and LUTs), BRAM usage, frequency, and efficiency using both LVT and XOR approaches. The XOR-based MPM module provides better performance than LVT-based MPM module. The 2W4R and 3W4R modules using LVT and XOR approaches are compared individually with existing similar MPM modules on the same FPGAs with better improvement hardware constraints.Keywords2W4R2W4RFPGALVTMultiported memoryXOR
Dynamic partial reconfiguration (DPR) enabled FPGA-based Cloud architecture acts as a flexible and efficient shared environment to facilitates application support to users’ request at low cost. While on one hand we need to handle a variety of tasks, such as periodic or sporadic, deadline or non-deadline, high or low critical tasks from the point of producing correct results, on the other hand we are constrained to use untrusted FPGA-based application IP blocks procured from various third-party vendors, which may contain hardware Trojan horse (HTH) affecting throughput and reliability of the Cloud. We propose Trojan-aware processing of tasks by monitored execution of a task on different untrusted cores, and then one more execution is done upon detection of hardware Trojan effects. For this stringent scheduling environment, the proposed dynamic scheduling algorithm is also properly extended to guarantee successful recovery from Trojan effects for all accepted tasks. Experimental results show that our algorithm improves worst-case-response-time for all tasks including non-deadline tasks and achieves lower task rejection rate for the deadline tasks, through judicious non-uniform partitioning of FPGAs based on supported jobs and subsequent better resource utilization, compared to that for existing Trojan-aware scheduling techniques.
High level synthesis (HLS) relies on the use of synthesis directives to generate digital designs meeting a set of specifications. However, the selection of directives depends largely on designer experience and knowledge of the target architecture and digital design. Existing automated methods of directive selection are very limited in scope and capability to analyze complex design descriptions in high-level languages to be synthesized using HLS. This article proposes a comprehensive model-based analysis framework, COMBA, which is capable of analyzing the effects of a multitude of directives related to functions, loops and arrays in the design description using pluggable analytical models, a recursive data collector and a metric-guided design space exploration algorithm. COMBA reports a small average error in estimating performance when compared with HLS tools like Vivado HLS, and finds a high-performance configuration of synthesis directives within minutes. Given different resource constraints, COMBA finds configurations with higher speed-ups, compared with the state-of-the-art. Moreover, COMBA can be used to guide the performance and area trade-off analysis. Experiments also show that our design space exploration algorithm outperforms the conventional genetic algorithm, and COMBA efficiently finds a near-optimal configuration, which proves the efficiency of our tool for optimizing the practical HLS based designs.
