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The underlying architecture of Xilinx 7 series FPGA depicts the underlying architecture of latest Xilinx 7 series 28nm FPGA chip. The basic constituent logic unit is called CLB (configurable logic block), arranged in a two-dimensional array on the chip, and can be connected through a programmable interconnect matrix. A CLB mainly consists of two slices. Each slice mainly consists of four 6-input LUTs, three multiplexers, one carry chain (CARRY4 in the dotted line), and eight storage elements (flip-flops). The 6-input LUT can implement any 6-variable logic function. There are two types of slice: the LUT in SLICEM can be configured as shift register logic (SRL) or general logic as needed, while the LUT in SLICEL can only be configured as general logic. These two slices are usually arranged in columns. This arrangement is called ASMBL architecture. Some compact PUF circuits can be designed based on some features of this architecture.
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Physical unclonable function (PUF) is a reliable physical security primitive. The Weak PUF and Strong PUF are two well-known PUF topologies. Strong PUF can be used to authenticate and protect intellectual property on FPGA chips. Classic PUF designs, like arbiter PUF, are hard to implement on FPGA and severely threatened by the machine learning base...
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... Notably, the ResNet network introduced the concept of residual blocks, enabling the training of deeper neural networks, which helps mitigate the vanishing gradient problem [14]. Work on FPGAs, which offer the advantages of low latency, low power consumption, and high flexibility over traditional hardware acceleration solutions, has been widely carried out [15][16][17][18][19][20][21][22][23][24][25][26][27]. However, they face limitations in on-chip resources, and modifications in network architecture necessitate hardware circuit redesign. ...
The ResNet series of networks has demonstrated powerful capabilities in the fields of object detection and image classification, garnering increasing attention from researchers. However, due to their deep network architectures, accelerator development based on FPGA faces challenges associated with limited on-chip resources and lengthy design cycles. This paper presents a versatile hardware acceleration system based on FPGA, achieving optimization through both hardware implementation and software inference architecture. The system reduces network complexity by employing techniques such as inter-layer fusion and dynamic quantization, while enhancing hardware resource utilization through channel parallelism and tightly-pipelined hardware design principles. By configuring and reusing computation units, the forward inference process of ResNet series networks can be rapidly deployed on FPGA, shortening the development and validation cycles. The proposed system is validated using the ResNet-18 model on a PYNQ-Z2 development board within a gesture recognition application scenario. The overall power consumption of the system is 2.136W, with hardware inference accuracy reaching 98.87%.
... In [14], a p-SPUF ("pseudo" Strong PUF) is proposed that combines Weak PUF with obfuscation logic in the form of shift registers. Although its simple architecture, it delivers good resistance to modeling attacks and smaller hardware overhead than typical Strong PUF designs. ...
Physical Unclonable Functions are security primitives that exploit the variation in integrated circuits’ manufacturing process, and, as a result, each instance processes applied stimuli differently. This feature can be used to provide a unique fingerprint of the electronic device, or as an interesting alternative to classic key storage methods. Due to their nature, they are often considered an element of the Internet of Things nodes. However, their application heavily depends on resource consumption. Lightweight architectures are proposed in the literature but are technology-dependent or still introduce significant hardware overhead. This paper presents a lightweight, Strong PUF based on ring oscillator architecture, which offers small hardware overhead and sufficient security levels for resource-constrained Internet of Things devices. The PUF design utilizes a Linear Feedback Shift Register-based scramble module to generate many challenge–response pairs from a small number of ring oscillators and a control module to manage the response generation process. The proposed PUF can be used as a Weak PUF for key generation or a Strong PUF for device authentication.
... This leads to significant optimization in hardware area and computational cost. Table 3 shows the hardware overhead and BER of the proposed PUF in comparison with other reliable PUF designs proposed in [43][44][45][46][47]. According to this table, not only does our design has lower BER but also outperforms the state-of-the-art in term of hardware overhead. ...
... With the deepening of research, different types of PUF circuits emerge in endlessly. There are many ways to classify PUFs, which are usually classified as weak or strong based on their ability to generate CRPs [5]. The CRPs generated by weak PUF are difficult to be obtained by the outside world and have a limited number, mainly including SRAM PUF [6], BR PUF [7], Glitch PUF [8], etc.; strong PUF can generate exponential number of CRPs, mainly including Arbiter PUF (APUF), MPUF [9] and IPUF [10]. ...
By using the XOR method to obfuscate response of Arbiter PUFs (APUFs), the ability to resist machine learning (ML) modeling attacks can be improved, but this method will reduce the stable of PUF to a certain extent, making PUF lose usability. In view of this, a highly stable XOR APUF (HS-XOR APUF) circuit is proposed by studying the generation mechanism of unstable response bits and the screening characteristics of the logic gates delay signals. First, the maximum and minimum delay signals are screened with AND/OR gate to generate highly stable response bits; Then, by inserting a inverter in the APUF switch unit, the delay time of the signal is increased, and the influence of environmental factors on the comparison signal with small delay deviation is weakened; Finally, the FPGA experimental results show that the response stability of HS-XOR APUF is rarely affected by the count of XOR units, and the AND/OR gate delay signal screening structure is simple and consumes a small amount of hardware resources, which can be widely used in the fields of information security.
... These responses with unpredictable, randomness, and unique chracterstics, which are suitable for the key generation, identification, authentication, and licensing fields. Various PUFs have been explored in the literature, and several security PUF-based solutions are proposed as the central building blocks in cryptographic protocols and security architectures [1]. ...
In this paper, we propose a novel modeling attack approach to predict the responses of XOR arbiter physical unclonable functions (XOR APUFs), which improves the prediction accuracy and reduces the computational time. The high-dimensional mathematical model of XOR APUF is established and its weakness is analyzed. Furthermore, a modeling attack approach based on the generalized regression neural network (MA-GRNN) is introduced to approximate the responses of XOR APUFs. As a proof-of-concept, four popular machine learning algorithms are utilized to evaluate the attack efficacy of 3-XOR, 4-XOR, 5-XOR and 6-XOR APUF schemes. Experimental results show that the MA-GRNN achieves a high prediction accuracy compared to the other three modeling attack approaches while requiring less computational time simultaneously.
... The difference between these two types is the ability to generate CRPs. Strong PUFs [7,8] obtain exponential CRPs through the reconstruction of hardware resources; however, the CRPs are correlated and more vulnerable to machine-learning attacks. Typical strong PUFs include arbiter PUF (APUF) [9,10] and ring oscillator PUF [11] (RO-PUF). ...
Owing to the large area and power consumption of traditional physically unclonable function (PUF)circuits, they are susceptible to interference from environmental factors. A compact PUF circuit design scheme is proposed by analyzing the circuit structure and sub-threshold leakage current deviation characteristics of a bistable PUF. First, the current-voltage sensitive characteristics of a transistor in the sub-threshold operating region are utilized. Next, to improve the output response speed and the uniqueness of the characteristic information of the PUF circuit, the proposed PUF circuit is designed which combines with the positive feedback and RS latch characteristics. Finally, simulation results based on the TSMC 65 nm CMOS process show that the PUF has good uniqueness, randomness, and reliability. The cell layout area, the bit error rate (BER) in the worst case, and the energy consumption are 0.177 μm², 2.8%, and 8.976 fJ/bit respectively.
... In addition, the work in [99] introduced parallel scan design based PUF and exploits the delay difference between pairs of shift registers as chains through the SR-Latch arbiter to reduce the area overhead and improve the uniqueness. Consequently, a combination of weak PUF and pseudo Strong PUF (p-SPUF) were proposed in [100]. The weak PUF produces 1-bit response from the variation process of the logic gates, which feeds as an input to the LFSR. ...
Physical Unclonable Function (PUF) has recently attracted interested from both industry and academia as a potential alternative approach to secure Internet of Things (IoT) devices from the more traditional computational based approach using conventional cryptography. PUF is promising solution for lightweight security, where the manufacturing fluctuation process of IC is used to improve the security of IoT as it provides low complexity design and preserves secrecy. It provides less cost of computational resources which prevent high power consumption and can be implemented in both Field Programmable Gate Arrays (FPGA) and Application-Specific Integrated Circuits (ASICs). In this survey we provide a comprehensive review of the state-of-the-art of PUF, its architectures, protocols and security for IoT.
To meet the demanding requirements of VLSI design, including improved speed, reduced power consumption, and compact architectures, various IP cores from trusted and untrusted platforms are often integrated into a single System-on-Chip (SoC). However, this convergence poses a significant security challenge, as adversaries can exploit it to extract unauthorized information, compromise system performance, and obtain secret keys. Meanwhile, traditional CMOS features have limitations in addressing hardware vulnerabilities and security threats, so promising post-silicon technologies offer potential solutions. Beyond-CMOS technologies offer avenues to fortify hardware security through distinct physical properties and nontraditional computing paradigms. These advancements bolster authentication processes, enhance key generation mechanisms, ensure hardware integrity and fortify resilience against side-channel attacks, hardware Trojans and quantum-resistant cryptography in securing hardware systems. This article provides a detailed review of hardware security, encompassing the identification and mitigation of threats, the implementation of robust countermeasures, the utilization of innovative primitives, countermeasures, various methodologies and distinct features offered by emerging technologies to resist hardware threats.Moreover, strategies to address challenges, explore future directions, and outline plans for achieving further research outcomes have been put forth in this field.
Security has become a main concern for the smart grid to move from research and development to industry. The concept of security has usually referred to resistance to threats by an active or passive attacker. However, since smart meters (SMs) are often placed in unprotected areas, physical security has become one of the important security goals in the smart grid. Physical unclonable functions (PUFs) have been largely utilized for ensuring physical security in recent years, though their reliability has remained a major problem to be practically used in cryptographic applications. Although fuzzy extractors have been considered as a solution to solve the reliability problem of PUFs, they put a considerable computational cost to the resource-constrained SMs. To that end, we first propose an on-chip-error-correcting (OCEC) PUF that efficiently generates stable digits for the authentication process. Afterward, we introduce a lightweight authentication protocol between the SMs and neighborhood gateway (NG) based on the proposed PUF. The provable security analysis shows that not only the proposed protocol can stand secure in the Canetti-Krawczyk (CK) adversary model but also provides additional security features. Also, the performance evaluation demonstrates the significant improvement of the proposed scheme in comparison with the state-of-the-art.
