Fig 1 - uploaded by Jiren Yuan
Content may be subject to copyright.
The spectrum of the sampled digital signal, the frequency responses of a zero−order−hold DAC and a linear interpolation DAC.
Source publication
A 10-bit, 100-MHz CMOS linear interpolation digital-to-analog converter (DAC) is presented. It includes a 16-tap voltage controlled delay line and a 10-bit binary-weighted DAC with a time-interleaved structure. The linear interpolation not only increases the attenuation of the DAC's image components, but also reduces the glitch of the binary-weight...
Contexts in source publication
Context 1
... DAC is developed in this design to realize a linear interpolation function, whose frequency response is approximately the square of the sinc function [1] [2]. Compared with the zero−order−hold DAC, the presented DAC can provide higher attenuation of the image signal, especially when the image components are near to the clock frequency. Fig. 1 shows the spectrum of the sampled digital signal, the frequency responses of a zero−order−hold DAC and a linear interpolation DAC. Moreover, as a result of the linear interpolation, the glitch of the binary−weighted DAC is reduced due to gradually turning on or off the current source of each bit. The proposed DAC has simple structure, ...
Context 2
... CMOS process, provided by AMS (Austria Mikro Systeme International AG). Fig. 8 shows the chip micrograph. The core size of the chip is 0.49mm x 0.52mm. The test setup is showed in Fig. 9. The full scale output is 490 mV, and the total power consumption is 86.5 mW. A measured sinewave spectrum for Fs=100 MHz and Fsig=7.37 MHz is shown in Fig. 10, the SFDR is 56.1 dB, the attenuation of the image signal is 45.35 dB. Fig. 11(a) and (b) shows the results of three tones measurement, the three signals are 7.39 MHz, 8.39 MHz and 9.39 MHz, respectively. The SFDR is 58 dB, as expected, the image attenuation at 7.39 MHz and 9.39 MHz are 40.5 dB and 44.6 dB, respectively. From the ...
Context 3
... Fig. 8 shows the chip micrograph. The core size of the chip is 0.49mm x 0.52mm. The test setup is showed in Fig. 9. The full scale output is 490 mV, and the total power consumption is 86.5 mW. A measured sinewave spectrum for Fs=100 MHz and Fsig=7.37 MHz is shown in Fig. 10, the SFDR is 56.1 dB, the attenuation of the image signal is 45.35 dB. Fig. 11(a) and (b) shows the results of three tones measurement, the three signals are 7.39 MHz, 8.39 MHz and 9.39 MHz, respectively. The SFDR is 58 dB, as expected, the image attenuation at 7.39 MHz and 9.39 MHz are 40.5 dB and 44.6 dB, respectively. From the measurement results, the attenuation of the image signal is doubled (dB) compared with ...
Similar publications
A new algorithm named the eight-section (ES) method for carrying out the interpolation for a magneto-resistive (MR) encoder is successfully developed and fabricated in a digital chip. It is known that a conventional magneto-resistive (MR) encoder employs the interpolation method, which converts incoming front-end analog signals in harmonics in sinu...
This paper presents a sigma-delta interface for fluxgate sensor based on a single-loop high-order modulation. A feedforward summation loop structure can reduce the linearity overload in integrators and the swing of integration signals. A Local feedback branch is proposed to realize the zero of noise transfer function (NTF) optimization and enhance...
This paper proposes a smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer. The technique accurately presets the frequency of VCO with small initial frequency error and greatly reduces the lock-in time. It can automatically compensate preset frequency variation with process and temperature. A 2.4 GHz synthesizer with 1...
In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 500 MSPS at 1.8 V is designed. The architecture of the proposed ADC is based on a Folding ADC with a cascaded-folding and a cascaded-interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the high-performanc...
This paper presents the design, architecture, and operation of a precision time interval and frequency counter made as a small, portable instrument with USB interface. Thanks to the use of advanced time interpolators designed in a CMOS chip, the precision (standard deviation) below 35 ps was obtained at measured time interval from 0 to 200 ms. The...
Citations
In a software-defined radio (SDR) system, the analog-to-digital converter (ADC) and digital-to-analog converter (DAC) should be fast and accurate enough for each communication standard. This chapter summarizes the requirements for the ADC and DAC in wireless systems. It discusses and compares different options to obtain a multi-mode system. The chapter describes briefly the requirements for reconfigurable systems. It focuses on the implementation of reconfigurable ADCs and DACs. The chapter deals with the implications of the SDR concept on data converters when more-or-less traditional transceiver concepts are used. Delta modulation; digital-analogue conversion; software radio; transceivers
This paper presents a low-complexity DDS IC for subcarrier processing in an FM-UWB transceiver. The IC implements data pre-filtering and FSK generation for the transmitter and quadrature LO signals generation for the receiver. The use of DDS techniques yields accurate signals whose parameters can be easily adjusted to accommodate a wide range of sub-carrier frequencies and bit rates. An interpolating DAC is used to directly generate the lowpass filtered analog output signals. The design will be fabricated in a standard 130 nm CMOS technology.
