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The resource utilization and power consumption in mW of the FPGA implementations of the proposed method.

The resource utilization and power consumption in mW of the FPGA implementations of the proposed method.

Source publication
Fig. 1: The Hadamard matrix H 8 and the codebook of Hadamard code (8,3)
Fig. 3: Overall hardware architecture for the proposed robust neural...
Fig. 7: The number of computed operations among the different numbers...
The number of clock cycles that perform error correction with different...
The resource utilization and power consumption in mW of the FPGA...
Robust Efficient Hardware Accelerator for Neural Network on Embedded System for Space Applications
Conference Paper
Full-text available
  • Sep 2022
The future of spacecraft missions will be populated with intelligent devices that require low-power hardware and a fault-tolerant platform. Deep neural networks are the state-of-the-art technique for machine learning tasks, which can be applied to large areas of application. However, these algorithms are both computationally intensive and radiation...
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Context 1
... the implementations are coded in VHDL and synthesized by the Xilinx Synthesis Tool that comes with Vivado 2021.2. Table 2 shows the utilization of an error correction engine with a 16-point Hadamard decoder and a Viterbi decoder that shared the same code rate. It is obvious that the Viterbi decoder consumes more power and utilization than the Hadamard decoder because the Viterbi decoder hardware is more general while the Hadamard decoder is limited to 16 bits of codewords. ...
Context 2
... is obvious that the Viterbi decoder consumes more power and utilization than the Hadamard decoder because the Viterbi decoder hardware is more general while the Hadamard decoder is limited to 16 bits of codewords. Moreover, the Table 2 also shows the utilization of neural inference engine with 14 × 14 MACC elements. It can clearly see that this hardware consumes more power due to its complexity. ...