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Reversible computations have attracted a lot of attention in recent years due to the ability to reduce energy dissipation that is needed in Nano circuits. The main purpose of designing reversible circuits is to reduce the energy consumption that occurs due to the loss of input bits in irreversible circuits. In this paper, we initially proposed a ne...
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... A single qubit can be characterized as a linear combination of the following ψ = α|0 + β|1 , where the probability amplitudes are α and β, and |α| 2 +|β| 2 = 1 [6]. Reversible computing is utilised in a variety of sectors, including smart city technology, optical computing, nanotechnology, the biomedical industry, and amongst others [7][8][9]. To synthesize a suitable reversible circuit, the designed circuit must have the lowest garbage output (GO), constant input (CI), and quantum cost (QC) [4,[9][10][11]. ...
... Reversible computing is utilised in a variety of sectors, including smart city technology, optical computing, nanotechnology, the biomedical industry, and amongst others [7][8][9]. To synthesize a suitable reversible circuit, the designed circuit must have the lowest garbage output (GO), constant input (CI), and quantum cost (QC) [4,[9][10][11]. The cost, which refers to the counting of (1 × 1 and 2 × 2) elementary quantum gates, is frequently used to determine implementation quantum costs. The quantum cost of any (1 × 1 and 2 × 2) gates is equal to one. ...
... As seen in Eqs. (5)(6)(7)(8)(9), the outputs are generated using Boolean expressions. ...
As a result of the recent development of quantum computers, there has been a rise in interest in both reversible logic synthesis and optimization strategies. Because every quantum operation is intrinsically reversible, there is a significant desire for research to create and optimize reversible circuits. This work suggests two novel reversible blocks with a low quantum cost. The reversible blocks are synthesized by an available synthesis technique that produces a grid list of multiple-control Toffoli gates. Then, the Toffoli-based grid is subjected to various optimization techniques, after which it is converted into a netlist of elementary quantum gates taken from the NCV (NOT, CNOT, Controlled-V, and Controlled-V⁺) library. In addition, a suggestion is presented for the creation of an unsigned multiplier that makes use of the functional blocks that are already available in the system. It has been found that the suggested designs are superior in terms of reversible metrics compared to the most cutting-edge techniques. Compared to recent works, the unsigned multiplier results in average savings of 14.43% for the quantum cost, 27.34% for the garbage output, and 23.29% for the constant input.
... [1][2][3][4] Recently, reversible-based designs have been growing interest as they have decreased heat dissipation. 5,6 Because energy loss is a critical concern with circuits that have been non-reversible. 7 As Landauer's research in the 1961 s suggested, information is lost in the form of heat when implementing classical circuits, regardless of technology. ...
... 13,14 Moreover, reversible logic can be used in a variety of applications, including low-power systems, quantum computing, nanotechnology, and fault tolerance systems. 6 Moreover, the performance of reversible circuits is evaluated using various measurement criteria such as garbage output (GO), constant input (CI), gate count (GC), and quantum cost (QC). Furthermore, GO indicates the number of outputs that are not used as the main outputs. ...
Reversible logic is used increasingly to design digital circuits with lower power consumption. The parity preserving (PP) property contributes to detect permanent and transient faults in reversible circuits by comparing the input and output parity. Multiplication is also considered one of the primary operations in both digital and analog circuits due to its wide applications in digital signal processing and computer arithmetic operations. Accordingly, Vedic mathematics, as a set of techniques sutras, has become popular and is extensively used to solve mathematical problems more efficiently and faster. This work proposes three PP reversible blocks, N1, N2, and N3, which are used to develop a novel effective 2‐bit PP reversible Vedic multiplier and 4‐bit ripples carry adders (RCAs). Moreover, 2‐bit Vedic multiplier and RCA are used to develop the 4‐bit PP reversible Vedic multiplier. The proposed designs outperform the most relevant state‐of‐the‐art structures in terms of garbage output (GO), constant input (CI), gate count (GC), and quantum cost (QC). Average savings of 22.37%, 35.44%, 35.44%, and 34.76%, and 17.76%, 26.60%, 24.52%, and 27.27% respectively, are observed for two‐bit and four‐bit PP reversible Vedic multipliers in terms of QC, GO, CI and GC as compared to previous works.
