The layout of a SRAM unit cell 

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... paper presents the design of a 128×12 SRAM block with each SRAM unit containing 2 pFET access transistors and a pre- charge-to-ground system for the purpose of minimizing its layout feature size. By using these techniques, the feature size of the SRAM cell with guard rings was effectively reduced to 12.6μm × 17.9μm, incorporating IBM SiGe5AM 0.5 μm process in order to make the SRAM suitable for extremely low temperature environment. To improve the reliability, several radiation hardening techniques have also been applied: guard rings were designed to separate pFET and nFET regions of the SRAM cell to prevent potential latch-up, and an error-correcting code (ECC) was also included to correct soft errors caused by ionizing radiation. Cryogenic testing has been performed to verify the SRAM is able to operate correctly over a temperature range of 2K to 297K. Memory is a necessary part of any microprocessor or microcontroller system. Static Random-access memory (SRAM) is often embedded in these systems as the main memory because of its short access time and high reliability. The proposed SRAM design is for extreme environment applications such as robotic and human explorations on the Moon and Mars. The specification requires the designed SRAM to be capable of operating reliably down to -180°C during the lunar night and -230°C in the shadowed polar craters in NASA’s planned lunar missions. In such a situation, the reliability of electronics in the spacecraft becomes one of the most important concerns. It has been well known that cryogenic operation of silicon CMOS technology can significantly improve the device performance [2]. Previous research on successful cryogenic circuit operation as well as radiation behavior has shown that SiGe BiCMOS processes are suitable for such extreme environments [3]. The IBM SiGe5AM process was selected, which has a 0.5 μm gate length and four layers of metal, including a thick AM layer [4]. Because of the limited number of metal layers, routing signals over the SRAM array is not allowed. Hot carrier injection at low temperatures is addressed by increasing the gate length of nFET devices [5-6]. The designed 128×12 SRAM block consists of a 15-bit shift register, a word line decoder, a bit line access X12 block, a 32×48 SRAM matrix, and an ECC unit as shown in Figure 2. Due to the limited space available on the chip for pin pads, a shift register was used to reduce pin count. The shift register outputs Y0~Y14 are used to supply the address and write data. The word line decoder is a 5-to-32 tree decoder using modified transmission gates to activate one row at a time. Transmission gate multiplexers are used to select the correct bit column. Each set of four bit columns are connected to an 8-to-2 multiplexer. The single output is connected to a pre-charge, write driver, and sense amplifier block to perform read and write operations to the addressed bit. The basic function of the bit line access blocks is to provide a digital interface between the SRAM array and the input/output processing. Hamming error correction codes are used to provide single bit error correction on data read from the SRAM array. During a write operation, the address and the write data are in the shift register. The write data, Y7~Y14, is fed into the ECC block, where four check bits are generated. After a period of time, the output of the ECC block will become valid, and the data word is ready to be written into the SRAM array. Proper operation of the ECC can be verified by evaluating DOUT0~11. The data address will be decoded, and the addressed data word can be activated by the row and column enable signals. Read operations follow a similar path, but only the address is used from the shift register. After the address is decoded, the sense amplifiers are enabled, and the data is read from the bit lines. The resulting data word is then fed into the ECC block, and check bits are generated and compared with the check bits present in the read data word. The differences are then compared, and the resulting syndrome is used to correct an error if one is present. If an error is detected, the corrected data can be written back into the original memory location directly by latching the corrected data and enabling the write drivers. The writing and reading operations will be further described in Section 3. The SRAM architecture used is a variation of the standard 6T cell [9]. Each SRAM bit consists of two cross-coupled inverters as a positive feedback loop, and two transistors to selectively access the two inverters. Due to the requirement of all nFET devices to use a gate length twice as wide as the process minimum, the drive strength of a nFET is only 1.5 times stronger than the drive strength of a pFET with the same width. This reduced the effective area penalty for using pFET devices for the access and drive transistors to only 12%. An additional benefit of using pFET devices as the main component in the SRAM cell is higher radiation tolerance. Off-state leakage currents increase on nFET devices after radiation bombardment, but pFET devices are largely unaffected. Excessive leakage in access transistors is highly undesirable and may cause data corruption. Usage of pFET access and devices should improve the total dose survivability of the SRAM. Transistor W/L ratios were designed with a signal to noise margin of 0.35V. Figure 3 indicates the final transistor sizing for the SRAM cell. The layout of the SRAM unit is shown in Figure 4. The bit cell is a mostly symmetrical design to keep the bit line true (BLT) and the bit line complimentary (BLC) parasitic effects as closely matched as possible. Power and ground wires are on the perimeter of the SRAM cell, which allows easy tiling of the cells as well as additional isolation between cells. V DD and ground wires are present on every metal layer to provide low resistance V DD and ground connections throughout the SRAM array. Cell size is reduced as much as possible, with a resulting size of 12.6μm×17.9μm. Guard-rings are added around the pFET and nFET regions to increase latch-up immunity from switching and ion impact transient conditions. The layout of a 128×12 SRAM block has a footprint of about 690×770 μm 2 . The bit line access block provides an I/O interface for the SRAM array. It consists of 12 bit line access units. During a write operation, the input data, WRD0-11, will be powered by the write driver and then loaded onto each bit line through a 4-to-1 multiplexer. While reading, the SRAM bit releases a data bit onto bit lines through the 4-to-1 MUX X2. Since there is a relatively large parasitic capacitance on bit lines, this output data can only make very small voltage difference on the bit lines. A sense amplifier is used to amplify this voltage difference to a full logic. This full logic output will then be sent out as output signal and written back into SRAM cell to restore the original data. The pre- charging network is used here to prevent accidentally writing during performance of reading operation. More design detail for each block will be given in the following subsections. When PRE-EN goes high prior to a read or write operation, all three transistors conduct and both BLT and BLC are pulled down to ground (logic 0). nFET N3 is used here to equalize the voltage on the two bit lines, which ensures proper operation of the sense amplifier. The equalization process is also improved. The sense amplifier provides a high impedance amplification path from the bit lines to a logic output. After the bit lines are pre- charged to 0V, the activated row will begin to pull one bit line towards V DD . Since a relatively large parasitic capacitance exists on the long bit lines, the voltage will change slowly. The sense amplifier generates a valid output without requiring the bit line to fully charge to V DD , which saves power and increases the read performance. There is no feedback signal from the output of the amplifier to the bit lines, so data corruption should not be an issue. The RD- EN signal switches the sense amplifier between an active sensing mode and a reset state. When RD-EN is high, the amplifier is deactivated, and the output nodes are discharged and equalized. This removes the bias towards the previous reading. Like the SRAM cell, the layout of the sense amplifier is as symmetrical as possible. When WR-EN goes high, the output of two NAND gates will be determined by the data to be written, WRD n. When WRD n is logic 1, pFET P1 will be open and connect BLT port to V DD . When WRD n equals 0, BLC will be connected to V DD . Special care was taken to ensure that the drive strength was high enough to write to the SRAM bits while traveling through the column multiplexer. ECC is used to provide a higher immunity against single event upsets (SEUs) and manufacturing defects. The ECC used is a (12, 8) Hamming code with single error correction (SEC). The ECC block diagram is given in Figure 10. A primary component is the Hamming code check generator (ECC_CHK_GEN). The check code generator produces the outputs required while minimizing the gate count and delay. When performing write operations, the signal RD/WR will be set to logic 0, and the ECC data path will be configured to generate the required check bits and place the check bits with the original data on the output, DOUT. The check code generator produces the following outputs. ...