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Maze routing algorithms are widely used for finding an optimal
path in detailed routing for very large scale integration, printed
circuit board and multichip modules. In this paper, we show that finding
an optimal route of a two-pin net in a multilayer routing environment
under practical via design rules can be surprisingly difficult. A
straightfor...
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Citations
... In addition, studies utilizing linear programming have been conducted to solve not only escape routing issues but also the maze routing problem [21] and global routing problem [22], [23], [24], [25]. In addition, Cong et al. [26] used Lagrangian relaxation (LR) to solve the routing problem while satisfying the length bound constraints. LR is a general technique that can be used to solve optimization problems with more complex constraints than ILP, by replacing each complex constraint with penalty terms in the objective function. ...
Circuit design plays an essential role in all consumer electronics products. Printed circuit board (PCB) and very-largescale integration (VLSI) circuit designing requires optimization of the electronic components placement and wire routing to connect the components. Currently, circuit routing processes have been performed manually by experts, which greatly increases the cost of human resources and time. Such heuristic circuit designs are not optimized and may have errors, which is why automated circuit routing algorithms are important. However, it is difficult to obtain an optimal solution in circuit routing as it is an NPhard problem. In addition, poor circuit routing increases the wire length of the circuit, which causes an increase in circuit cost and weight as well as performance degradation. In order to achieve routing optimization, many technologies have been proposed, in which some have applied artificial intelligence (AI) to improve the overall performance and reduce the designing time. Accordingly, in this paper, routing problems in PCB and VLSI are explained, and proposed technologies to solve these routing problems are introduced. Especially, a detailed investigation and analysis of AI technologies grafted into circuit routing algorithms are explained, and the considerations for AI-based routing algorithms are presented.
... As shown in the previous section, the feeding and shorting vias are the key components of the proposed multi-layer dipoles and could significantly influence their performance. However, the characteristics of on-wafer vias are noticeably different from the ideal ones with neglectable losses, especially in the microwave band or above their contact resistance and losses could be very significant [29][30] . In this 0.18 m μ CMOS process, only one type of via with a dimension of 2 0.28 0.28 m μ × is available for connecting the metal layers, and its typical DC resistance is somewhat large as 6.5 Ω , but its RF resistance is not provided in the brochure. ...
A novel multi-metal-layer dipole antenna, in which some identical dipoles are deployed on different metal layers and effectively connected by the feeding and shorting vias, is proposed for wireless inter-/intraconnects. An accurate equivalent model is also presented for better understanding of its physical fundamentals. Simulations show that a six-layer dipole typically has a size reduction of 13.0% and a bandwidth enhancement of 35.3% compared with the corresponding one-layer dipole. An example chip carrying one- and six-layer dipoles was also fabricated through a 0.18-¿m mixed-mode process and on-wafer characterized with full two-port measurements. The experimental results show that further size reduction and bandwidth enhancement could be obtained due to the loadings of lossy vias in six-layer dipoles, and the transmission coefficients of multilayer dipoles could also be improved for the in-phase additive contributions of dipoles on different layers. The propagation mechanisms of wireless intraconnects were evaluated and discussed with the assistance of path-loss coefficient ¿, and it is revealed that the propagation is mostly through the surface waves when the dipole operate far below its resonant frequency, while the space-wave propagation would dominate when approaching the resonant frequency.
... 53 kontaktierung zu realisieren. Auf Basis des rasterfreien 2D-Routingalgorithmus DUNE [13], [14], [15], [16] wurde ein 3D-Routingalgorithmus entwickelt, der nicht nur die Vor teile der Hadlock-und Hightower-Algorithmen besitzt, sondern auch das Routing inner halb eines Körpers ermöglicht. ...
Im Rahmen der Arbeit wurde ein integriertes 3D-MIDCAD-System vorgestellt, welches die besonderen Anforderungen der MID-Konstruktion berücksichtigt und die bisher getrennten ECAD- und MCAD-Umgebungen zusammenführt. Das Ziel der Arbeit war es, mit dem MIDCAD-System einen Beitrag für eine innovative MID-Produktentwicklung zu liefern, um die Entwicklungszeit und damit die Kosten zu senken und gleichzeitig die Produktstruktur zu optimieren und damit die Produktqualität zu erhöhen.
... There is an abundance of research on this problem, starting with maze search on graphs [6] [10]. Much of the work on area routing has focused on improving the speed of maze routing, and adding consideration of physical constraints [8,5]. While finding a path between a pair of points can be time consuming, and efficient implementation of the algorithms is difficult, there are satisfactory solutions to this problem. ...
Interconnect delay dominates system delay in modern circuits, and with reduced feature sizes, coupling capacitance and signal crosstalk have become significant issues. By spacing interconnect wires effectively, and avoiding long parallel runs, coupling can be reduced; with current routing methods, however, this is difficult to achieve. In this paper, we present a new approach to area routing. Rather than inserting routes sequentially (using a performance driven maze router), multiple candidate routes for each connection are generated; excess routes are then eliminated iteratively. Experiments show that we obtain substantial reductions in coupling capacitance, without sacrificing routing completion rates.
... A straightforward implementation of the shortest path algorithm for directed acyclic graph (DAG) has a complexity of time. 7 Since the coarse routing graph is very dense [i.e., ], the complexity for the algorithm is about , which can be time consuming. Because the special cost structure of the CPPA problem, we are able to find efficient algorithms (linear time in practice) for the shortest path problems in CPPA. ...
This paper presents a new pseudopin assignment (PPA) algorithm
with crosstalk noise control in multilayer gridless general-area
routing. We propose a two-step approach that considers obstacles and
minimizes the weighted sum of total wire length and the estimated number
of vias under crosstalk noise constraints. We test our algorithms on a
set of MCM examples and a set of standard-cell examples. Without
crosstalk noise control in PPA, the average noise in the MCM test cases
after detailed routing is 0.13-0.22 V<sub>DD</sub> with up to 11% of
nets larger than 0.3 V<sub>DD</sub>. However, if the noise constraint of
each net is set to 0.3 V<sub>DD</sub> in PPA, the average noise in each
case reduces to 0.11-0.15 V<sub>DD</sub> (15%-31% reduction) with no
crosstalk noise violations. Most of the nets in our standard-cell test
cases do not have noise problems. Our PPA algorithms still give better
noise distributions and have 1%-10% noise reduction on the global nets
in these standard-cell test cases. Even without ripup and reroute, the
detailed routing completion rate is 93%-99% and the average vias per net
is only 0.7-1.4 for our MCM test cases and 1.0-1.7 for our standard-cell
test cases
... The special nets are fixed in the subsequent routing; therefore they become obstructions. To handle complicated obstructions, maze searching is the most commonly adopted technique [1,4,14,1718192021222325]. A maze router is able to find the shortest path from a given source to a given target, if the path exists. ...
A new routing algorithm is presented. It is based on a multiple star net model, force-directed placement and maze searching techniques. The algorithm inherits the power of maze routing in that it is able to route complex layouts with various obstructions. The large memory requirement of the conventional maze algorithm is alleviated through successive net refinement, which constrains the maze searching to small regions. The algorithm shows advantages in routing designs with complicated layout obstructions
... We conclude our paper in Section V. An extended abstract of this work was published earlier in the Proceedings of the 1999 International Symposium on Physical Design [8]. ...
Maze routing algorithms are widely used for finding an optimal path in detailed routing for VLSI, PCB and MCMs. In this paper, we show that finding an optimal route of a two-pin net in a multi-layer routing environment under practical via design rules can be surprisely difficult. Furthermore, a straightforward extension to the maze routing algorithm that disallows via-rule incorrect routes may either cause a suboptimal route to be found, or more seriously, cause the failure to find any route even if one exists. We present a refined heuristic to this problem by embedding the distance to the most recently placed via in an extended connection graph so that the maze routing algorithm has a higher chance of finding a via-rule correct optimum path in the extended connection graph. We further present efficient data-structures to implement the maze routing algorithm without the need to preconstruct the extended connection graph. Experimental results confirmed the usefulness of our algorithm an...
Design rule (DR) is the most critical challenge for generating a cell layout automatically in the advanced process technologies (e.g., finFET-EUV). Previous works explicitly encode the complicated DRs into routing constraints and automation scripts, which may not be general and efficient for addressing the DR problem. Therefore, an automatic cell layout generation (ACLG) framework is proposed and adopts three implicit-learning techniques [i.e., guidance learning (EGL), DR learning (DRL), and mistake-driven learning (MDL)], which jointly discover the knowledge of complex DRs from the existing layouts in the cell library. EGL learns the geometry behavior of the target metals from the legal cell layouts. DRL learns the DRs from layout patterns. MDL learns the routing constraints iteratively from the encountered mistakes during the layout generation (LG). These three implicit-learning techniques are combined into ACLG and developed into four core stages to cope with the DR challenge in a more general and efficient way. The experimental results demonstrate that ACLG effectively solves all the DR violations (DRVs) in an advanced finFET-EUV process (100% success rate on fixing DRVs) and successfully yields DRC-clean cell layouts for 13 benchmark cells. In addition, the proposed DRL technique is more efficient than the commercial DRC tool in excluding the illegal layout solution space. The number of iterations for a generated legal cell layout is reduced by 30% on average with DRL (3.31) compared to the commercial DRC tool (4.69). Moreover, the total runtime of generating legal layouts for 13 benchmark cells is further improved by
$2.57\times $
on average. Since DRL not only reduces the iterations of refining the DRVs in the generated cells but also speedups the process of DR checking (DRC) efficiently.
