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In this paper, reduction logical operator (RLO) has been proposed to control bottleneck link size by realizing Multi-Valued Logic (MVL) function. A novel Switch Delay Link Mechanism (SDLM) Algorithm using Transmission Control Protocol (TCP) has been represented to serve as a basic input generator for base and reduced link size of the network bottle...
Citations
... Therefore, In this paper, an effort of reduced neural logic operators is considered for synthesizing MVL functions. MVL synthesis and its application covers a wide range of topics [4][5]. ...
In this paper, a Neural Network Deployment (NND) algorithm is presented to realize and synthesize Multi-Valued Logic (MVL) functions. The algorithm is combined with back-propagation learning capability and MVL operators. The operators are used to synthesize the functions. Consequently the synthesized expressions are applied by the MVL neural operators. The advantages of NND-MVL algorithm are demonstrated by accuracy measurement of MVL neural operator realization. Furthermore, evaluation of NND-MVL algorithm is analyzed by its application, propagation delay and accuracy achieved for training with 4 hidden neurons. In a brief, an effort of training MVL neural operators and utilizing them for logic synthesis is observed.
A voltage-mode three transistor based MAX circuit for implementation of multi-valued logic (MVL) system is proposed in this paper. The proposed MAX operates at very low power consumption ranging in micro watts. To evaluate MAX performance, a NOR gate realization is done and compared to standard CMOS NOR gate. The HSpice simulation result confirms the MAX based NOR gate to operate with minimal delay at low power level. The simulations have been performed on 180nm technology.
