Figure 4 - A New Approach for a Unified Architecture for Type IV DCT/DST with an Efficient Incorporation of Obfuscation Technique

The VLSI architecture of the hardware core that implements Equation (11), where * marks a delay of one clock cycle [26].

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Reference

A New Approach for a Unified Architecture for Type IV DCT/DST with an Efficient Incorporation of Obfuscation Technique - Scientific Figure on ResearchGate. Available from: https://www.researchgate.net/figure/The-VLSI-architecture-of-the-hardware-core-that-implements-Equation-11-where-marks-a_fig1_353219417 [accessed 30 Jun, 2024]

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Figure 4. The VLSI architecture of the hardware core that implements Equation (11), where * marks a delay of one clock cycle [26].

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<a href="https://www.researchgate.net/figure/The-VLSI-architecture-of-the-hardware-core-that-implements-Equation-11-where-marks-a_fig1_353219417"><img src="https://www.researchgate.net/publication/353219417/figure/fig1/AS:1045144094654487@1626193178925/The-VLSI-architecture-of-the-hardware-core-that-implements-Equation-11-where-marks-a.png" alt="The VLSI architecture of the hardware core that implements Equation (11), where * marks a delay of one clock cycle [26]."/></a>