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![The VLSI architecture of the hardware core that implements Equation (11), where * marks a delay of one clock cycle [26].](publication/353219417/figure/fig1/AS:1045144094654487@1626193178925/The-VLSI-architecture-of-the-hardware-core-that-implements-Equation-11-where-marks-a.png)
The VLSI architecture of the hardware core that implements Equation (11), where * marks a delay of one clock cycle [26].
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This paper aims at solving one challenging problem in designing VLSI chips, namely, the security of the hardware, by presenting a new design approach that incorporates the obfuscation technique in the VLSI implementation of some important DSP algorithms. The proposed method introduces a new approach in obtaining a unified VLSI architecture for comp...
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In this paper, we propose a new hardware algorithm for an integer based discrete cosine transform (IntDCT) that was designed to allow an efficient VLSI implementation of the discrete cosine transform using the systolic array architectural paradigm. The proposed algorithm demonstrates multiple benefits specific to integer transforms with efficient h...
This paper introduces an efficient solution for designing a unified VLSI implementation for type IV DCT/DST while solving one challenging problem in obtaining high performance VLSI chips for common goods, which is solving the security of the hardware while obtaining a VLSI implementation with high performance. The new solution uses a new systolic a...
Citations
... There are very many good VLSI implementations for type II and type III DCT, and quite a few good hardware implementations for type IV DCT or type IV DST [20][21][22][23][24][25][26][27][28][29]. Among them, there are only a few unified solutions that can efficiently execute both transforms using a large portion of the area in common on the same chip [20][21][22]28]. ...
... There are very many good VLSI implementations for type II and type III DCT, and quite a few good hardware implementations for type IV DCT or type IV DST [20][21][22][23][24][25][26][27][28][29]. Among them, there are only a few unified solutions that can efficiently execute both transforms using a large portion of the area in common on the same chip [20][21][22]28]. ...
... In [28], is the authors presented a unified VLSI architecture for type IV DCT/DST that is the best reported in the literature, whereas we have eight computational structures implemented using eight short systolic arrays and where 2(N − 1) general multipliers and 2(N − 1) adders have been used. Because it uses general multipliers with a higher hardware complexity as compared to multipliers with a constant, it has a significantly higher hardware complexity. ...
This paper introduces an efficient solution for designing a unified VLSI implementation for type IV DCT/DST while solving one challenging problem in obtaining high performance VLSI chips for common goods, which is solving the security of the hardware while obtaining a VLSI implementation with high performance. The new solution uses a new systolic array algorithm for type IV DST that can allow us to obtain an efficient unified VLSI architecture with one previously designed for type IV DCT. The proposed method uses special arithmetic structures that have been called quasi-cycle convolutions that can be efficiently mapped on linear systolic arrays. Moreover, the obtained unified VLSI architecture, besides being an efficient implementation with a low hardware complexity and high-speed performance, allows for an efficient inclusion of the obfuscation technique with very low overheads.
... These architectures have several merits over others, especially due to their regular and local data flow with an efficient input/output and data transfer operations, as in case of systolic arrays architectures. Thus, we have obtained efficient VLSI implementations of certain digital signal processing (DSP) algorithms that are using cyclic convolutions or circular correlations [23][24][25][26][27] that have been extended to some other regular and modular computational structures, such as, for example, skew-circular and pseudo-circular correlations or band-correlations [28][29][30]. ...
... Due to the unique characteristics of the utilized computational structure, it becomes feasible to efficiently integrate the obfuscation hardware security technique using methods similar to the ones described in [30]. ...
In this paper, we present two systolic array algorithms for efficient Very-Large-Scale Integration (VLSI) implementations of the 1-D Modified Discrete Sine Transform (MDST) using the systolic array architectural paradigm. The new algorithms decompose the computation of the MDST into modular and regular computational structures called pseudo-circular correlation and pseudo-cycle convolution. The two computational structures for pseudo-circular correlation and pseudo-cycle convolution both have the same form. This feature can be exploited to significantly reduce the hardware complexity since the two computational structures can be computed on the same linear systolic array. Moreover, the second algorithm can be used to further reduce the hardware complexity by replacing the general multipliers from the first one with multipliers with a constant that have a significantly reduced complexity. The resulting VLSI architectures have all the advantages of a cycle convolution and circular correlation based systolic implementations, such as high-speed using concurrency, an efficient use of the VLSI technology due to its local and regular interconnection topology, and low I/O cost. Moreover, in both architectures, a cost-effective application of an obfuscation technique can be achieved with low overheads.
... In [1], Chiper and Cotorobai try to resolve one challenging problem in designing VLSI chips for embedded designs used in DSP applications, namely, an efficient incorporation of the security techniques, while maintaining the high performances of these chips. They propose a new approach for designing a unified VLSI architecture for discrete sine and cosine transforms of type-IV (DCT/DST IV), which allows an efficient incorporation of the obfuscation technique. ...
In the new era of digital revolution, the digital sensors and embedded designs become cheaper and more present [...]
... There are several VLSI implementations for direct and inverse DCT [17][18][19][20][21][22][23][24][25][26][27], but only a few optimal VLSI implementations for type IV DCT or type IV DST [28][29][30][31][32][33][34][35][36][37][38]. Until now, there is no efficient VLSI implementation for type IV DCT or type IV DST that allows an efficient implementation of a hardware security technique, excepting our papers [31,32]. ...
... There are several VLSI implementations for direct and inverse DCT [17][18][19][20][21][22][23][24][25][26][27], but only a few optimal VLSI implementations for type IV DCT or type IV DST [28][29][30][31][32][33][34][35][36][37][38]. Until now, there is no efficient VLSI implementation for type IV DCT or type IV DST that allows an efficient implementation of a hardware security technique, excepting our papers [31,32]. ...
... The same property is true for the elements on the lines parallel with the main diagonal. In this matrix-vector product, the vector has constant elements as opposed to the case presented in [32] where these elements are variable. This property can be exploited to significantly reduce the hardware complexity of the VLSI implementation. ...
This paper aims to solve one of the most challenging problems in designing VLSI chips for common goods, namely an efficient incorporation of security techniques while maintaining high performances of the VLSI implementation with a reduced hardware complexity. In this case, it is very important to maintain high performance at a low hardware complexity and the overheads introduced by the security techniques should be as low as possible. This paper proposes an improved approach based on a new VLSI algorithm for including the obfuscation technique in the VLSI implementation of one important DSP algorithm used in multimedia applications. The proposed approach is based on a new VLSI algorithm that decomposes type IV DCT into six quasi-cycle convolutions and allows an efficient incorporation of the obfuscation technique. The proposed method uses a regular and modular structure called quasi-cyclic convolution and the obtained architecture is based on the architectural paradigm of systolic arrays. In this way we can obtain the advantages introduced by systolic arrays, especially high speed, with an efficient utilization of the hardware structure. Moreover, using the proposed VLSI algorithm, we can obtain the important benefit of attaining hardware security. Thus, a more efficient VLSI architecture for type IV DCT can be obtained, with a significant reduction of the hardware complexity, and an efficient incorporation of an improved hardware security mechanism with low overheads. These features are very important for resource-constrained common goods.
... This allow a significant reduction of the hardware complexity. As it can be seen from equations (6), (9), (11), (16) and (17), the number of multiplications is significantly reduced in a such way that instead of 64 multiplications from equation (3) we are using only 7 simple multipliers with small integers represented on 6 bits. The pre-processing and post-processing stages are used to implement the equations (7)-(10, (12)-(15) and (18),(19) ,which are only additions and subtractions and are used to compute the input and the output sequences. ...
... Moreover the proposed solution has all the advantages of using modular and regular computational structures as cycleconvolution and circular correlation in the VLSI implementation of the discrete transforms as regularity, modularity and local interconnections and also a high throughput specific to systolic arrays by using pipelining and parallelism. Moreover, due to the specific form of the computational structure used called quasi-cycle convolution it is possible to efficiently implement a hardware security technique called obfuscation using similar ideas as presented in [16]. ...
In this paper we propose a new VLSI algorithm for an integer based discrete sine transform (IntDST) that allows an efficient VLSI implementation using systolic arrays. The proposed algorithm have all the benefits of an integer transform as a good approximation of irrational transform coefficients and allows an efficient restructuring into a regular and modular computation structure that allows an efficient VLSI implementation using systolic arrays. An efficient VLSI architecture for discrete sine transform can be obtained that allows an efficient incorporation of the obfuscation technique that significantly improves the hardware security and offering high speed performances due to a concurrent computation and using pipelining technique at a low hardware complexity.
