Fig 4 - uploaded by Ayman Ismail
Content may be subject to copyright.
![The Termination technique of [21]. (a) Actual circuit. (b) Simplified model.](profile/Ayman-Ismail-6/publication/245344828/figure/fig4/AS:624485233356800@1525900290620/The-Termination-technique-of-21-a-Actual-circuit-b-Simplified-model.png)
Source publication
![Fig. 4. The Termination technique of [21]. (a) Actual circuit. (b)...](profile/Ayman-Ismail-6/publication/245344828/figure/fig4/AS:624485233356800@1525900290620/The-Termination-technique-of-21-a-Actual-circuit-b-Simplified-model_Q320.jpg)
In this work, a new termination technique for the averaging network of the flash analog-to-digital converter (ADC) input preamplifiers is devised. The proposed technique eliminates the over-range voltage headroom consumed by the dummy preamplifiers and therefore, the input capacitance and power dissipation of the ADC is reduced. This technique is a...
Contexts in source publication
Context 1
... Fig. 3 only one edge of the preamplifiers array is shown, and it is assumed that number of dummy preamplifiers per edge are used to eliminate the edge problem. The number of needed dummy preamplifiers is reduced by altering the value of the averaging resistors at the edge, as suggested in [21] [ Fig. 4(a)]. The output voltage of the dummy amplifier in ...
Similar publications
A new non-linearity reduction technique for stochastic flash ADC (SF-ADC) is proposed, focusing on distribution of comparator inputreferred offsets. The SF-ADC test chip fabricated in a 130-nm CMOS process demonstrated the proposed technique can improve SNDR. In addition, the digital re-quantization also can improve the linearity more, where quanti...
This paper describes a novel energy-efficient, high-speed ADC architecture combining a flash ADC and a TDC. A high conversion rate can be obtained owing to the flash coarse ADC, and low-power dissipation can be attained using the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is proposed to achieve high linearity. A test chip was fa...
Analogue-to-digital converters (ADC) using oversampling technology and the Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using a discrete second-order feedforward structure. A 5-bit successive approximation register (SAR) quantizer is inte...
This work presents a design of 6-bit, 1 Gs/s, low power (less than 100 mW), low offset, low area, high resolution, high speed, and flash ADC data converter. To reach these specifications, a high-speed multiplexer, comparator, and encoder are to be designed. A conventional 6-bit flash type converter requires 2⁶ resistors for ladder network and 2⁶ −...
Citations
... High speed analogue-to-digital converters (ADCs) are used in variety of applications like wireless communication systems (Cmos et al., 2014), ultra-wideband (UWB) radios (Cao et al., 2009), direct-sampling TV receivers and digital broadband applications (Stepanovic and Nikolic, 2012), digital oscilloscopes (Jiang et al., 2010), serial-link receivers (Tseng et al., 2014), optical signal processing (Ismail and Elmasry, 2008), disk-drive electronics (Mehr and Dalton, 1999), nuclear instrumentation applications like noise spectroscopy (Langeveld et al., 2013), time-of-flight mass spectrometer , BaF2 detector array (Wang et al., 2017), Doppler broadening spectroscopy (Cizek et al., 2011), HPGe detectors (Mihailescu et al., 2007), non-intrusive cargo inspection (Kwong and Langeveld, 2016), positron-lifetime spectroscopy (Bečvář et al., 2005) and many others. ...
... The logarithm function is used to maintain a relatively small score range. Figure 5 shows calculated scores for most of the flash ADCs reported in the literature [5,7,8,10,11,[13][14][15]18,20,22,23,25,26,28,29,31,35,37,38,40,41,[43][44][45][46][47][49][50][51]53,54,56,57,59,[61][62][63][64][65]67,68,70,72]. ...
In this work we introduce the flash ADC design automation (FADA) framework. It aims to reduce the design time of the threshold inverter quantization (TIQ) flash ADCs and optimizes the selected TIQ comparators of the flash ADC for differential nonlinearity (DNL), integral nonlinearity (INL), analog voltage range, power consumption and comparator noise values. We performed a survey study on flash ADCs published in the last two decades and compared them to our 10-bit single-channel TIQ flash ADC. Further, it took FADA < 6 h to design the 10-bit TIQ flash ADC compared to few weeks of manual design. Accordingly, FADA selected TIQ comparators set for the 10-bit TIQ flash ADC with DNL and INL values less than 0.17 LSB and 0.16 LSB, respectively, when designed in the ibm65n CMOS technology. The 10-bit TIQ flash ADC has simulated signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) values of 57.2 dBs and 61 dBs, respectively. It consumes 1.67 mW of power and operates at 1.57 GSample/s. FADA provides TIQ models to optimize for high-performance versus low-noise TIQ flash ADCs designs.
... The dynamic performance with varying supply voltages have been incorporated in Figure 15 as discussed in the following subsection. It is found to be 14 fJ/conv which is 44% more as compared to [18] and comparable to [19] and [24] as seen from Figure 16. Deguchi et al have designed a faster flash ADC involving a pre-amplifier that allows the ADC to operate at higher sampling rate but the resolution is limited to moderate range. ...
... [1][2][3][4] In this case, gray ROM-based encoder, 4 because of the regularity of the encoder structure and the need for only local connections to perform thermometer codes to 1-of-N codes conversion, is used extensively in 5-bit°ash ADCs and higher ones and is used to implement the encoder block of°ash ADCs in Refs. [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23]. So, in this paper the gray ROM-based encoder is called as the conventional encoder. ...
In this paper, gray ROM-based encoder is proposed for the implementation of flash ADCs encoder block based on converting the conventional 1-of-N thermometer codes to 2-of-M codes (M=34N). The proposed gray ROM-based encoder is composed of three stages. In the first stage, the thermometer codes are converted to 2-of-M codes by the use of two-input AND and four-input merged AND-OR gates. In the second stage, 2-of-M codes are turned to n-1 gray codes and a binary code by a quasi-gray ROM encoder and a binary ROM encoder, respectively. Finally, in the third stage, n-1 MSB bits and LSB bit are determined by a quasi-gray-to-binary converter and a CMOS inverter, respectively. The advantages of the proposed encoder over the conventional encoder are higher speed of second stage, low power, low area and low latency with the same bubble and meta-stability errors removing capability. To demonstrate the mentioned specifications, two 5-bit flash ADCs with the conventional and proposed encoders in their encoder blocks are analyzed and simulated at 2-GS/s and 3.2-GS/s sampling rates in 0.18-μm CMOS process. Simulation results show that the ENOBs of flash ADCs with the conventional and proposed encoders are equal. In this case, the proposed encoder outputs are determined to be approximately 30ps faster than the conventional encoder at 2 GS/s. The power dissipations of the conventional and proposed encoders were 19.50mW and 13.90mW at 3.2-GS/s sampling rate from a 1.8-V supply and also the latencies of the encoders were 4 ADC clocks and 3 ADC clocks, respectively. In this case, the number of D-FFs and logic gates of the proposed encoder is decreased approximately by 37% when compared to the conventional encoder.
... High sampling rate (1-3 GS/s) analog-to-digital converters (ADCs) with medium resolutions (6-10 bits) are utilized in diverse applications, including wireless communication systems [1,2], ultra-wideband (UWB) [3], direct-sampling TV receivers [4,5], and digital oscilloscopes [6]. Other applications of these wideband ADCs are in high-speed communication systems such as serial-link receivers [7,8], optical communications [9], and the read channels of disk drives [10][11][12]. Designing energy-efficient wideband ADCs is essential, especially for portable battery-powered devices. ...
... Flash, folding, and interpolating ADC architectures are inherently suitable for high-speed analog-to-digital conversion. However, for medium resolutions and above, their power efficiency degrades significantly due to the large number of active comparators, [9,13,14,77,78]. For pipelined ADCs, high-performance design becomes more difficult as scaled CMOS supply voltages continue to decrease due to the stringent gain and bandwidth requirements for the opamps. ...
This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6–8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics.
... An ADC accepts an analog input, a voltage or a current, and converts it to a digital word that can be read by a microprocessor. The flash ADC is the fastest type available [1], which is used in wireless communication [7], ultra pulse signal generation, optical communication link, radar detection and ultra wide band receivers [4] & [5]. ...
... In this paper, the analog input range detection circuits are replaced by the proposed digital ones based upon comparators to enhance the bandwidth and to decrease the power dissipation. The proposed circuit employs the conventional averaging techniques [2][3][4][5] in flash ADC to reduce the offset voltage of pre-amplifiers and to improve the nonlinearity. In section 2, the proposed ADC architecture and the proposed digital range detector circuit block are explained in details. ...
A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process. © 2014, Institute of Electronics Engineers of Korea. All rights reserved.
... In this paper, the analog input range detection circuits are replaced by the proposed digital ones based upon comparators to enhance the bandwidth and to decrease the power dissipation. The proposed circuit employs the conventional averaging techniques [2][3][4][5] in flash ADC to reduce the offset voltage of pre-amplifiers and to improve the nonlinearity. In section 2, the proposed ADC architecture and the proposed digital range detector circuit block are explained in details. ...
A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82mW with a single power supply of 1.2V and achieves 4.9 effective number of bits for input frequency up to 1MHz at 500 MS/s. Therefore it results in 4.75pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.
... The above mentioned issues tighten the design trade-o®s between precision, power, speed, and die area of ADCs. 2,4,8,14,15 Flash ADC known as the fastest ADC type is the most competent option for the aforementioned applications. [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] Although the°ash resolution is limited due to the exponential increase in circuit die area and consumed power per each extra bit of resolution, the parallel topology of°ash assists the achievement of very high operation speeds. ...
... 2,4,8,14,15 Flash ADC known as the fastest ADC type is the most competent option for the aforementioned applications. [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] Although the°ash resolution is limited due to the exponential increase in circuit die area and consumed power per each extra bit of resolution, the parallel topology of°ash assists the achievement of very high operation speeds. 3,[5][6][7][8]11 Meanwhile, the parallel topology increases the input capacitance (C in ) of the ADC that limits the bandwidth of the ADC at higher resolutions. ...
... Practically, with the submicron CMOS technology, not only the possible large C in but also the low voltage supply and input o®sets are the main obstacles for°ash ADC bandwidth-accuracy product. 2,14,15 O®set averaging technique is an e±cient method to increase both the linearity/accuracy and bandwidth but it costs large power consumption and circuit complexity. [1][2][3][4]6,7,[10][11][12][13][14][15][16]20 In this case, interpolation with inherent o®set averaging is a more quali¯ed method that results in such further advantages as power reduction, bandwidth and accuracy enhancement especially where combined with resistive averaging. ...
In this work, a 6-bit 1.33 GS/s flash analog-to-digital converter (ADC) is proposed. To noticeably save the power and area and greatly increase the speed, compactness and accuracy its complete structure is elaborately implemented in MOS Current Mode Logic (MCML) topology. The proposed ADC does not use a front-end track and hold (T/H) block either. Furthermore, a novel optimized resistance ratio averaging-interpolation scheme is applied to: (1) reduce the offset, nonlinearity, number of preamplifiers, area and the power (2) increase the accuracy and mismatch insensitivity (3) minimize the size of elements towards the more compact size, smaller area and higher speed for the ADC. To maximize all these achievements, most favorably, it is completely built by NMOS transistors realizing the ever desired unique NMCML (NMOS-MCML) structure. Using intermediate gray encoding and exponential gains by extra latches greatly removes the bubble/meta-stability error and increases both the speed and the accuracy. Utilizing a differential ladder and some other deliberate arrangements reduces the kickback noise and common mode interferences, minimizes the structure and facilitates fast recovery of overdrive signals. The proposed ADC is simulated by Hspice using 0.18 μm TSMC technology and shows; effective resolution band width (ERBW) larger than 903 MHz that is 1.36 times more than Nyquist frequency (fs/2), 35.17 dB/49.4 dB SNDR/SFDR, 5.53 bits ENOB (rather flat SNDR and ENOB from 50 MHz to 750 MHz), and the low power consumption of 37.77 mW from a 1.2 V supply. These results prove that applying so many effective and novel plans has obtained a unique all N-MCML flash ADC with power-efficiency of 0.61 pJ per conversion step. Both Monte Carlo and corner cases simulations in addition to temperature analysis are performed that prove both intra-die and inter-die robustness of the proposed structure.
... Typically, comparators are dominant in power consumption of flash ADCs due to the essential gain to suppress the offset [9], [10] and their large quantity. Since the main objective of the proposed architecture is to achieve low-power operation, minimum-size transistors are used in the comparator without preamplifier and the offset is calibrated. ...
... The thresholds in each comparator are generated by sizing the unbalanced transistor with its gate connected to properly. Assuming first that the currents in both branches are at a well balance condition, the relationship between the size of and the comparator's threshold can be derived as follows: (10) with , M1 and M2 all operating in saturation region in this instance: (11) Therefore, the threshold voltage of the comparator (with the length and width of M1 and M2 are identical) is given by (12) Since the overdrive voltage of is large , an unbalance can be easily generated with a small size of which reduces the speed and area penalty of adding an extra transistor. Even though this technique may degrade the power supply rejection ratio (PSRR) of the comparator circuit, it is well suited for low-resolution and high-speed ADCs. ...
This paper presents a 5-bit 1.25-GS/s folding flash ADC. The prototype achieves a folding factor of four with a capacitive folding technique that only consumes dynamic power. Incorporated with various calibration schemes, folding errors and the comparator's threshold inaccuracies are corrected, thus allowing a low input capacitance of 80 fF. The design is fabricated using 65-nm digital CMOS technology and occupies 0.007 mm 2. The maximum DNL and INL post calibration are 0.67 and 0.47 LSB, respectively. Measurement results show that the ADC can achieve 1.25 GS/s at 1-V supply with a total power consumption of 595 μW. In addition, it exhibits a mean ENOB of 4.8b at dc among ten chips, which yields an FoM of 17 fJ/conversion-step.
