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A common way of improving an application's performance is implementing it on a custom hardware. High level synthesis (HLS) and application specific instruction-set processor are two alternatives for automating this process. HLS techniques usually can handle small programs. Also, since the datapath is not available during scheduling, limited datapat...
Citations
... They are all conceptually similar but can differ in the scope of optimizations they perform on input code and the allowed level of user interventions. One of them, No-Instruction- Set Computer (NISC) is developed at the UCI Center for Embedded Computer Systems [7]. It is a C-to-Verilog compiler that assumes user customizable processor architecture as input, besides the input C code. ...
The needs for automated digital system design rise with constant technology improvements and time-to-market shortening. High-level synthesis tools cope with this problem by raising the design specification to a higher level. We have implemented the methodology of custom processor automated modeling for DCT algorithm. This algorithm is often used in signal and image processing applications. At front end, the methodology assumes C code input specification as it is the case of many high-level synthesis tools. C programming language popularity offers the applicability for a broader spectrum of users. At back end, logic synthesis tools produce the FPGA implementation of the algorithm. The results are evaluated in terms of execution cycles required for completing the algorithm and processor's datapath components allocations, and compared to previous work.
Trade-off between execution time and resource occupation arise in all kinds of digital system designs. Here we present such relation for FPGA-based custom processor design. Usually, the optimal tradeoff is directed by device sizing on all scales of the design, but for FPGA device, as predefined hardware platform, it is more focused on comparison of existing platforms organizations. The customization of processor architecture as a point of design performance improvement is usually focused on selection of parameter set that governs the most the design characteristics. In this paper, the focus is on processor architecture datapath with predefined design template and relationship of its structure to final FPGA implementation it maps to. For purpose of evaluation of multiple design at the same time, the appropriate software flow is applied to construct the design space based on constraining of datapath functional units operation types. The data are collected throughout the whole design flow starting from input control and data flow characteristics of the application and ending with FPGA implementation data. The analysis of the design flow showed dependence of final implementation on datapath structure and its components complexities.
The automation of custom hardware design often focuses on hardware optimizations for smaller portions of code that dominate the design execution. The same presumption can be stated for custom processor design. The data path of the processor can be well optimized for particular blocks of code that are formed during control flow extraction. However, larger source codes can have tens of blocks that result from Control Flow Graph (CFG). We implemented a global semi-automated flow that hierarchically forms the set of blocks which contributions are modeled into processor architecture. Resulting processor model is translated to RTL description and implemented inside FPGA logic.
