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The Low Power Wireless Processor

The Low Power Wireless Processor

Source publication
Figure 1. The Low Power Wireless Processor
Figure 2. Partitions of the AMBA interface with 2 DSP IPs
Figure 3. Timing diagram for data transfer from the LEON Processor to...
Figure 4. The Power Distribution of the Main Blocks
Low Power System-on-Chip Platform Architecture for High Performance Applications
Article
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  • Jan 2002
This paper describes work on the development of a scheme for implementation of low power high p erformance Digital Signal Processing intensive AMBA based System-On-Chip platforms. The scheme is based on a novel interfacing scheme which utilises the bus hierarchy within AMBA in order to allow single and multiple high p erformance DSP Intellectual Pr...
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Contexts in source publication

Context 1
... overall SoC platform architecture is demonstrated in Figure 1. The architecture is built around the LEON processor, and includes a number of high performance DSP IP cores. ...
Context 2
... illustrated in Figure 1, the scheme in this paper can allow multiple high performance IP cores to be attached to the platform. In this paper only a single DSP IP core is used to demonstrate the above scheme. ...