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The 8-bit AES encryption core architecture with iterative structure and simple clock gating technique
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... this paper, AES encryption core processes data in 128-bit blocks with the key lengths of 128-bit. To reduce the AES encryption core area, we employ an 8-bit architecture with an optimized S-box so that the AES core encrypts an 8-bit data block in each clock cycle. The proposed AES encryption core architecture is shown in Fig. 1. This core includes a key expansion unit, a mixcolumn unit, a parallel to serial converter and a byte permutation unit. S-box 1 and S-box 2 blocks are the sub-blocks in the byte permutation unit and key expansion unit as described in ...
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... a low power consumption implementation, a simple clock gating technique is proposed by using start_in signal as shown in Fig. 1. The clock tree in the AES core is controlled by this signal. S-box is an important block in the AES core so that some papers on S-box optimization for the specific requirements have been published [2][3][4][5]. To reduce the complexity, we use the S-box architecture with the direct hardware implementation. In this paper, the S-box is ...
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... Decode-Switch-Encode (DSE), which is employed by [3], [12], is another method for implementation Sub-Bytes that is a good option for low-power architecture; however, it occupies a larger area. The efficient way of implementing Sub-Bytes is to use composite field arithmetic, such as [7], [13] [14]. Sub-Bytes contains calculating the multiplicative inverse of ...
... Previous works such as [13] used LUT for their RCON. Van-Phuc et al. [14] optimized the RCON block by using the simple Karnaugh optimization. Hamalainen et al. [22] implemented RCON by using the round counter and combinational logic. ...
... There were a big 32 × 8-bit RAM and one internal register to store the intermediate results in [26]. Van-Phuc et al. [14] did not explain more details about their architecture. However, their architecture had an 8-bit datapath that contained two Sub-Bytes, a Mix-Columns block with two 8-bit outputs, a parallel-to-serial converter, and a byte permutation unit. ...
Due to the fast-growing number of connected tiny devices to the Internet of Things (IoT), providing end-to-end security is vital. Therefore, it is essential to design the cryptosystem based on the requirement of resource-constrained IoT devices. This article presents a lightweight advanced encryption standard (AES), a high-secure symmetric cryptography algorithm, implementation on field-programmable gate array (FPGA) and 65-nm technology for resource-constrained IoT devices. The proposed architecture includes 8-bit datapath and five main blocks. We design two specified register banks, Key-Register and State-Register, for storing the plain text, keys, and intermediate data. To reduce the area, Shift-Rows is embedded inside the State-Register. To adapt the Mix-Column to 8-bit datapath, we design an optimized 8-bit block for Mix-Columns with four internal registers, which accept 8-bit and send back 8-bit. Also, a shared optimized Sub-Bytes is employed for the key expansion phase and encryption phase. To optimize Sub-Bytes, we merge and simplify some parts of the Sub-Bytes. To reduce power consumption, we apply the clock gating technique to the design. Application-specific integrated circuit (ASIC) implementation results show a respective improvement in the area over the previous similar works from 35% to 2.4%. Based on the results, the proposed design is a suitable cryptosystem for tiny IoT devices.
... On the other hand, recently, silicon on thin buried oxide (SOTB) CMOS is an advanced technology for the ultra-low-power integrated circuit (IC) design and a good candidate for low-power electronics [12]. In [13], a compact design of 8 bit AES encryption core in 65 nm SOTB CMOS was presented with synthesis-based results. However, detail design tradeoffs and more improvements are expected, especially with silicon demonstration. ...
The design of ultra-low power advanced encryption standard (AES) encryption cores for emerging wireless networks and Internet of things systems by combining optimised architectures, a simple clock gating technique and an advanced 65 nm silicon on thin buried oxide (SOTB) CMOS process is presented. The implementation results show that the proposed 2-Sbox AES encryption core requires the smallest number of clock cycles and achieves the lowest power consumption of 0.4 µW/MHz which is 3.3× lower than that of the best previous presented AES encryption core, with a very small area overhead. Moreover, the proposed 1-Sbox AES encryption core consumes very low hardware resources of 2.4 kgates gate equivalent.
The hardware footprint for S-box specification in lightweight block cipher as appropriate to IoT and CPS information security systems is presented in this paper. The S-box Boolean function in the lightweight block cipher is defined using the Reed-Muller structure. A Rule Based–Common Sub-structure Sharing Optimization (RB-CSSO) algorithm has been proposed towards improving the performance efficiency of Reed-Muller structure. This novel hybrid RB-CSSO optimization mechanism first transforms the direct Positive Polarity Reed Muller (PPRM) S-box representation into Mixed Polarity Reed-Muller (MPRM) S-box architecture using local rule based transformation. Secondly, the Common Sub Term (CST) and Common Sub-expression (CSE) merging/elimination are employed over the resulting MPRM structure. The combined rule-based transformation and the common sub-function sharing demonstrate an overall reduction in area, delay and power of the Reed-Muller S-box structure. Both the theoretical analysis and the experimental verification demonstrate reduction in area and delay of S-box. Post synthesis results based on ASIC standard cell based implementations have been used to analyze area, delay and power values across Process, Voltage and Temperature (PVT) corners for a wide range of operating conditions. Extensive comparisons between direct PPRM and optimized MPRM implementations have been carried out. The post layout simulations of S-box structures realized show the advantages of lower area-delay product, power-area product and power-delay product. This work thus authenticates the application of proposed structure for lightweight, resource constrained security systems. Industry standard full suite of Cadence® tools have been employed in the simulations using 65 nm TCBN65GPLUS standard cells of TSMC technology library.
