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This paper proposes the use of four-transistor (4T) cache and branch predictor array cell designs to address increasing worries regarding leakage power dissipation. While 4T designs lose state when infrequently accessed, they have very low leakage, smaller area, and no capacitive loads to switch. This short paper gives an overview of 4T implementat...
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... 4T DRAM cells are well established and described in introductory VLSI textbooks [18]. 4T cells are similar to ordinary 6T cells but lack two transistors connected to Vdd that replenish the charge that is lost via leakage ( Figure 1). Using exactly the same transistors as an optimized 6T design, the 4T cell requires only 59% of the cell area [5]. ...
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Citations
... Another significant problem in deep submicron technologies is the problem of leakage [10]. Recent work attacks the leakage problem using architectural techniques [12,13,14,15] but does not fully address leakage variation with temperature. Many of these techniques would benefit from run-time adjustments to account for leakage change. ...
... 4T sensors can also provide leakage measurements to adjust leakage-saving techniques to ever-changing leakage conditions. In the Cache Decay [14] and related work [12,15] a simplifying assumption was that leakage currents were constant. The trade-off of power-savings for performance-loss was only balanced for a specific leakage rate. ...
We present a novel temperature/leakage sensor, developed for high-speed, low-power, monitoring of processors and complex VLSI chips. The innovative idea is the use of 4T SRAM cells to measure on-chip temperature and leakage. Using the dependence of leakage currents to temperature, we measure varying decay (discharge) times of the 4T cell at different temperatures. Thus, decaying 4T sensors provide a digital pulse whose frequency depends on temperature. Because of the sensors' very small size, we can easily embed them in many structures thus obtaining both redundancy and a fine-grain thermal picture of the chip. A significant advantage of our sensor design is that it is insensitive to process variations at high temperatures. It is also relatively robust to noise. We propose mechanisms to measure temperature that exploit the sensor's small size and speed to increase measurement reliability. Decaying 4T sensors also provide a measurement of the level of leakage at their sensing area, allowing us to adjust leakage-control policies. Our 4T sensors are significantly smaller, faster, more reliable, and power efficient compared to the best previously proposed designs enabling new approaches to architectural-level thermal and leakage management.
With semiconductor technology advancing toward deep submicron, leakage energy is of increasing concern, especially for large on-chip array structures such as caches and branch predictors. Recent work has suggested that larger, aggressive branch predictors can and should be used in order to improve microprocessor performance. A further consideration is that more aggressive branch pre-dictors, especially multiported predictors for multiple branch prediction, may be thermal hot spots, thus further increasing leakage. Moreover, as the branch predictor holds state that is transient and predictive, elements can be discarded without adverse effect. For these reasons, it is natural to consider applying decay techniques—already shown to reduce leakage energy for caches—to branch-prediction structures. Due to the structural difference between caches and branch predictors, applying decay techniques to branch predictors is not straightforward. This paper explores the strategies for exploiting spatial and temporal locality to make decay effective for bimodal, gshare, and hybrid predictors, as well as the branch target buffer (BTB). Furthermore, the predictive behavior of branch predictors steers them towards decay based not on state-preserving, static storage cells, but rather quasi-static, dynamic storage cells. This paper will examine the results of implementing Authors' addresses: • 181 decaying branch-predictor structures with dynamic—appropriately, decaying—cells rather than the standard static SRAM cell. Overall, this paper demonstrates that decay techniques can apply to more than just caches, with the branch predictor and BTB as an example. We show decay can either be implemented at the architectural level, or with a wholesale replacement of static storage cells with quasi-static storage cells, which naturally implement decay. More importantly, decay techniques can be applied and should be applied to other such transient and/or predictive structures.
Understanding the performance impact of compiler optimizations on superscalar processors is complicated because compiler optimizations interact with the microarchi- tecture in complex ways. This paper analyzes this interaction using interval analysis, an analytical processor model that allows for breaking total execution time into cycle components. By studying the impact of compiler optimizations on the various cycle components, one can gain insight into how compiler optimizations affect out-of-order processor performance. The analysis provided in this paper reveals various interesting insights and suggestions for future work on compiler optimizations for out-of-order pro- cessors. In addition, we contrast the effect compiler optimizations have on out-of-order versus in-order processors.
Energy efficient and performance efficient instruction fetch unit is a critical issue in modern processor design. Trace cache
which stores dynamic basic-block stream can significantly improve performance efficiency. Conventional trace cache (CTC) usually
adopts set associative structure which requires probing all the data ways in parallel such that only the output of the matched
way is used, but the energy for accessing the other ways is wasted. In this paper, we propose a selective way based trace
cache (SWTC), which probes only the selected way(s) instead of probing all the data ways. In SWTC, traces are divided into
several types and stored into cache by type. Then the trace cache is partially activated and accessed. Based on these design
principles, a SWTC model is proposed and evaluated in this paper. Simulation results show that compared to CTC, SWTC can reduce
energy consumption on the fetch unit by 20.1% on average, while providing almost the same performance in terms of number of
instructions per cycle.
With semiconductor technology advancing toward deep submicron, leakage energy is of increasing concern, especially for large on-chip array structures such as caches and branch predictors. Recent work has suggested that larger, aggressive branch predictors can and should be used in order to improve microprocessor performance. A further consideration is that more aggressive branch predictors, especially multiported predictors for multiple branch prediction, may be thermal hot spots, thus further increasing leakage. Moreover, as the branch predictor holds state that is transient and predictive, elements can be discarded without adverse effect. For these reasons, it is natural to consider applying decay techniques---already shown to reduce leakage energy for caches---to branch-prediction structures.Due to the structural difference between caches and branch predictors, applying decay techniques to branch predictors is not straightforward. This paper explores the strategies for exploiting spatial and temporal locality to make decay effective for bimodal, gshare, and hybrid predictors, as well as the branch target buffer (BTB). Furthermore, the predictive behavior of branch predictors steers them towards decay based not on state-preserving, static storage cells, but rather quasi-static, dynamic storage cells. This paper will examine the results of implementing decaying branch-predictor structures with dynamic---appropriately, decaying---cells rather than the standard static SRAM cell.Overall, this paper demonstrates that decay techniques can apply to more than just caches, with the branch predictor and BTB as an example. We show decay can either be implemented at the architectural level, or with a wholesale replacement of static storage cells with quasi-static storage cells, which naturally implement decay. More importantly, decay techniques can be applied and should be applied to other such transient and/or predictive structures.
