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The 16-Bit Carry Select Adder Is Divided By The Carry Ripple Adder Into 4 Parts, While Each Part Consists Of A Duplicated 4-Bit Carry Ripple Adder Pair.
Source publication
In this paper, we proposed an area-efficient carry select adder by sharing the common Boolean logic term. After logic simplification and sharing partial circuit, we only need one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation. Through the multiplexer, we can selec...
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Citations
... The summation result is prepared before the input carry signal accomplishes; hence in every single bit adder, an accurate computation result is arrived by waiting for only one multiplexer delay. In the CSA, the CPD may be decreased by M times than the RCA [4], [12]. ...
... In this paper, we suggested an area-proficient CSA by sharing the common Boolean logic. After Boolean simplification, [12]. ...
... Before the carry in signal arrive summation is ready. Here in CSLA, only need to wait for the multiplexer delay in every single bit adder [14]. Carry propagation delay can reduce by 'N' times than RCA. ...
... After Boolean simplification, duplicated adder in conventional CSLA can be removed. Correspondly in every single bit adder block duplicate carry out and sum signal can be generated [14]. Here in conventional CSLA, original characteristics of parallel architecture can presented by utilize the multiplexer to choose the precise output according to its preceding carry output signal. ...
... Here in conventional CSLA, original characteristics of parallel architecture can presented by utilize the multiplexer to choose the precise output according to its preceding carry output signal. Hence circuit area, transistor count and power delay product of the circuit can be decreased to a great extent [14]. These characteristics make it more area efficient and power proficient [3]. ...
... Ripple Carry Adder is composed of many cascaded single-bit full adders. The circuit is simple and areaefficient but computation speed is slow [2]. Carry Look-Ahead Adder derives faster results but there is increase in area. ...
Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in data-processing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is designed by using single Ripple Carry Adder(RCA) and Binary to Excess-1 Converter (BEC) instead of dual RCAs in order to reduce the area and power consumption with small speed penalty. CSA and MCSA structures are designed for 8-bit, 16-bit, 32-bit and 64-bit. Result analysis shows that MCSA is better than CSA.
