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This paper presents a high-throughput and routing complexity reduced decoder for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes in the high rate wireless personal area network applications (WPAN). Our selected code is the rate-1/2 QC-LDPC code in IEEE P802.11ad/D1.0. A new decoder architecture is proposed. The message paths between variable...
Contexts in source publication
Context 1
... parity check matrix of an LDPC code can be illustrated graphically using a tanner graph [8] shown in Fig. 1. Each bit is represented by a variable node (a circle in the figure and referred to as a VN), and each parity constraint is represented by a check node (a square in the figure and referred to as a CN). An edge exists between a variable node i and a check node j if and only if H(j, i) = 1, and no nodes of the same type can directly ...
Context 2
... consists of sixteen submodules and each submodule is responsible for a VN. Each submodule consists of four ECNFUs, which is in charge of a neighboring CN of the VN. The structure of ECNFU is shown in Fig. 10, where new v2c 1 [3 : 0] is the message to the CN. Its first three bits are the magnitude and last bit is the sign. The first and second minima and the product of signs are from NRC, and the newly updated results will be written back to NRC. When all of VNs are processed, every CN has obtained the first and second minima of magnitudes ...
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Citations
... Efficient implementations for high-rate QC-LDPC codes and area-efficient architectures are described in Refs. [20,21]. However, for fully parallel implementations, QC-LDPC codes do not retain the same low decoding complexity advantages. ...
One of the attractive features of low-density parity-check (LDPC) codes is the parallel iterative nature of their iterative belief propagation decoding, making them amenable to efficient hardware implementation. However, for an arbitrary code construction, the random-like connections between the code's Tanner graph variable and check nodes makes fully-parallel implementation a difficult task as this leads to complex interconnect wiring and routing congestion. In this paper, we present a novel LDPC code design approach, based on the progressive edge growth (PEG) Tanner graph construction, to solve the problem of dense connections between processing nodes. The approach is based on controlling the maximum connection length between processing nodes in order to make fully parallel implementation feasible. The proposed algorithm offers a good compromise between error correction performance and decoder complexity. Simulation results and FPGA-based implementation comparisons are presented to demonstrate the advantages of the proposed LDPC code constructions, and it is shown that, with proper window-constrained node placement design, an improvement of up to 40% in interconnect efficiency is achievable without any significant degradation in error correction capability.
This paper presents a generic RAM based FPGA architecture for decoding of Multi Rate Quasi-Cycling LDPC codes. RAM based decoding enables us to reduce permutation networks into simple address controllers. Moreover, utilizing Block RAMs with various aspect ratios in an FPGA provides flexibility ranging from area driven compact designs to fully parallelized high throughput designs. Utilizing the read-first property of the RAMs, the proposed design efficiently exploits the dual port Block RAM resources by accessing all the four ports at the same time. Such facilities of recent FPGA devices have been combined with the well known layered decoding algorithm with non-linearly mapped Min-Sum approximation in order to obtain area efficient yet high throughput decoders. The proposed decoder architecture has been verified on Xilinx XC7Z020 FPGA device for IEEE 802.16e Wimax LDPC codes. 340Mbps of information throughput has been observed at an operating frequency of 150MHz.
