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TSV metallization: a) Cu Seed layer via MOCVD and b) completely filled TSV via ECD blanket process and sidewall metallization via pattern plating, respectively
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3D integration technologies show increasing importance for high volume applications while realizing the smallest system dimensions at least. Therefore vertical interconnect and wafer bonding technologies were optimized and adapted to reach a high yield using quite narrow contact areas and bond frames. These technologies must enable mechanical stabl...
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Context 1
... to PVD processes CVD is more capable of metalizing TSV's with very high aspect ratio (up to 20) [9]. An example of a MOCVD seed layer for a TSV with an AR of 10 is shown in Fig 1a. The electroplating is carried out in a RENA EPM 201F. ...
Context 2
... is carried out in a RENA EPM 201F. A photo resist pattern serves as mask for pattern plating to simultaneously deposit the TSV and the redistribution layer. Hence, further metal patterning processes or as well as planarization, respectively could be avoided. A major issue for large TSV's is their cross sectional design and type of metallization (Fig. 1b). A complete filling with copper has the advantage of a low resistance and a perfect sealed package. Moreover, from process point of view, a completely filled TSV could be more easily connected from the wafer backside when thinning is done after TSV fabrication. However, major drawback of such TSV's is the stress issue and the need for ...
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Citations
... The fabrication of through wafer vias with high aspect ratio and via filling technologies is the critical process to realize vertical electrical interconnect, which has two important technologies including through silicon via (TSV) and through glass via (TGV). However, in TSV interconnects, additional submicron-thick isolated layer is required to be deposited [9], and the difficulty for this is in the void-free conformal coating of high aspect ratio vias to avoid isolation failure [5,10]. Besides, the signal crosstalk induced by parasitic capacitance coupling between electrical feedthroughs and bulk silicon substrate also limits the application of TSV technology. ...
Taking advantage of good hermeticity, tiny parasitic capacitance, batch mode fabrication, and compatibility with multiple bonding techniques, the glass-silicon composite substrate manufactured by the glass reflow process has great potential to achieve 3D wafer-level packaging for high performance. However, the difference in etching characteristics between silicon and glass inevitably leads to the formation of the undesired micro-protrusions near the silicon-glass interface when preparing a shallow cavity etched around a few microns in the composite substrate. The micro-protrusions have a comparable height with the depth of the cavity, which increases the risks of damages to sensitive structures and may even trigger electrical breakdown, resulting in thorough device failure. In this paper, we studied the characteristics of the chemical composition and etching mechanisms at the interface carefully and proposed the corresponding optimized solutions that utilized plasma accumulation at the interface to accelerate etching and bridge the gap in etching rates between different chemical compositions. Finally, a smooth transition of 131.1 nm was achieved at the interface, obtaining an ideal etching cavity surface and experimentally demonstrating the feasibility of our proposal. The micromachining solution is beneficial for improving the yield and structural design flexibility of higher performance micro-electromechanical systems (MEMS) devices.
... To overcome this problem, typical bonding technologies using sputtered Cu require liquid treatment before inserting wafers to a bonding chamber. The other methods are heating at 350 • C or higher and formic acid gas introduction inside the bonding chamber just before the bonding process [13]. However, high temperature is not desired for temperature-sensitive devices. ...
... Majority of the hermetic packaging technologies through thermo-compression bonding involved Au [17,18], Cu [13][14][15][16] or Al [19,20] layer for sealing rings, which are deposited by either magnetron sputtering or evaporation. Such deposition processes are able to realize a high-quality, flat bonding interface, which is essential for thermo-compression bonding [21]. ...
Hermetic packaging plays an important role for optimizing the functionality and reliability of a wide variety of micro-electro-mechanical systems (MEMS). In this paper, we propose a low-temperature wafer-level hermetic packaging method based on the thermo-compression bonding process using an electroplated Cu sealing frame planarized by a single-point diamond mechanical fly-cutting. This technology has an inherent possibility of hermetic sealing and electrical contact as well as a capability of integration of micro-structured wafers. Hermetic sealing can be realized with the sealing frame as narrow as 30 μm at a temperature as low as 250 °C. At such a low bonding temperature, a less amount of gases is desorbed, resulting in a sealed cavity pressure lower than 100 Pa. The leak rate into the packages is estimated by a long-term sealed cavity pressure measurement for 7 months to be less than 1.67 × 10−15 Pa m3 s−1. In addition, the bonding shear strength is also evaluated to be higher than 100 MPa.
... On the other hand, Cu is known as a low-cost material and is widely used in the back-end process of semiconductor manufacturing. However, low-temperature vacuum sealing by thermo-compression bonding using Cu frames is difficult, because the native oxide layer on the Cu surface, which cannot be removed below 350 • C, prevents Cu atomic diffusion for achieving strong bonding strength [10,11]. Thus, Cu surface pre-treatment to remove the native oxide layer must be employed for low-temperature vacuum bonding. ...
A novel surface activation technology for Cu-Cu bonding-based wafer-level vacuum packaging using hot-wire-generated atomic hydrogen treatment was developed. Vacuum sealing temperature at 300 °C was achieved by atomic hydrogen pre-treatment for Cu native oxide reduction, while 350 °C was needed by the conventional wet chemical oxide reduction procedure. A remote-type hot-wire tool was employed to minimize substrate overheating by thermal emission from the hot-wire. The maximum substrate temperature during the pre-treatment is lower than the temperature of Cu nano-grain re-crystallization, which enhances Cu atomic diffusion during the bonding process. Even after 24 h wafer storage in atmospheric conditions after atomic hydrogen irradiation, low-temperature vacuum sealing was achieved because surface hydrogen species grown by the atomic hydrogen treatment suppressed re-oxidation. Vacuum sealing yield, pressure in the sealed cavity and bonding shear strength by atomic hydrogen pre-treated Cu-Cu bonding are 90%, 5 kPa and 100 MPa, respectively, which are equivalent to conventional Cu-Cu bonding at higher temperature. Leak rate of the bonded device is less than 10−14 Pa m3 s−1 order, which is applicable for practical use. The developed technology can contribute to low-temperature hermetic packaging.
... At least a 350 • C bonding temperature with post-bond annealing is necessary to obtain good bonding strength [7]. Baum adopted two pre-treatment processes before Cu-Cu bonding to achieve hermetic sealing [8]. Rebhan used different pre-treatments to decrease the bonding temperature significantly [9]. ...
... At least a 350 °C bonding temperature with post-bond annealing is necessary to obtain good bonding strength [7]. Baum adopted two pre-treatment processes before Cu-Cu bonding to achieve hermetic sealing [8]. Rebhan used different pre-treatments to decrease the bonding temperature significantly [9]. ...
To increase the yield of the wafer-level Cu-Cu thermo-compression bonding method, certain surface pre-treatment methods for Cu are studied which can be exposed to the atmosphere before bonding. To inhibit re-oxidation under atmospheric conditions, the reduced pure Cu surface is treated by H 2 /Ar plasma, NH 3 plasma and thiol solution, respectively, and is covered by Cu hydride, Cu nitride and a self-assembled monolayer (SAM) accordingly. A pair of the treated wafers is then bonded by the thermo-compression bonding method, and evaluated by the tensile test. Results show that the bond strengths of the wafers treated by NH 3 plasma and SAM are not sufficient due to the remaining surface protection layers such as Cu nitride and SAMs resulting from the pre-treatment. In contrast, the H 2 /Ar plasma–treated wafer showed the same strength as the one with formic acid vapor treatment, even when exposed to the atmosphere for 30 min. In the thermal desorption spectroscopy (TDS) measurement of the H 2 /Ar plasma–treated Cu sample, the total number of the detected H 2 was 3.1 times more than the citric acid–treated one. Results of the TDS measurement indicate that the modified Cu surface is terminated by chemisorbed hydrogen atoms, which leads to high bonding strength.
... One requirement of the Via Middle approach is the establishment of a mechanical and electrical contact upon WLB to the MEMS wafer. For this purpose, Cu Thermo-Compression Bonding (TCB) has been identified as promising method [9]. It provides good mechanical strength for the desired hermetically sealing of the MEMS device and it is compatible to the Cu TSV technology. ...
Aluminum, copper, and gold are commonly used metallization materials for microelectronic and micro electro mechanical system applications. Typically metal wafer bonding technologies are diffusion‐based methods. Metal‐based wafer bonding uses relatively low temperatures. Solid liquid interdiffusion bonding (SLID) is a possible way to bond at a low temperature with a resulting interface that is stable at temperatures higher than the bonding temperature. Besides semiconductor wafer substrates, other materials can also be used with SLID bonding, example, ceramics or glasses. At first Cu/Sn SLID bonding was used in the field of 3D integration by using solder balls. Metal thermocompression bonding is a form of solid state bonding, more specifically diffusion bonding. The bonding happens in three phases: interface formation, grain reorientation, and grain growth. A eutectic is a mixture of two materials that solidifies or melts at a temperature that is lower than the melting temperature of each material.
Metal-Metal diffusion bonding was reassuring for micro electro mechanical system (MEMS) packaging and three dimensional (3D) integration. Despite copper and gold, aluminum (Al) is also proficient for wafer-level bonding due to its CMOS compatibility. As of now, a successful bonding reported with a temperature requirement is >300 °C, due to chemically unwavering surface oxide on the aluminum surface. In this work, a facile method of successful Al-Al bonding at a low temperature and pressure by passivating Al surface with another ultrathin noble metal has been reported. Here, a systematic study for selecting a required optimum ultrathin passivation layer thickness in making the surface to be free from surface oxide formation is provided. Also, looking over in an enhancement of surface morphology and microstructure by varying the thickness of an ultrathin passivation layer. Added to this, after obtaining the required oxide-free surface, we conducted wafer-level thermo-compression bonding for optimizing low temperature (~250 °C) and pressure (~3 MPa) by inspecting interface quality and reliability studies. We put forward that the proposed bonding technique is promising to use at the wafer-level, to integrate high-performance chip stack interconnects and facile packaging methods for micro-electro-mechanical systems.
This paper reports a novel wafer-level heterogeneous integration and vacuum packaging technology by thermo-compression bonding using electroplated Cu frame planarized by fly-cutting. High grain boundary density on the Cu surface induced by fly-cutting process enables vacuum bonding at temperature as low as 250°C, achieving less than 100 Pa sealed cavity pressure. Availability of the technology for microstructured wafers is also demonstrated, yielding bonding shear strength higher than 200 MPa.
Developing 3D systems is still not matured yet in semiconductor industry. Next to several open questions regarding the selection of a suitable technology, test has gained much significance, since several new test moments are involved. In this paper the different domains of the development process of a 3D-integrated heterogeneous system are analyzed. Finally, a tool will be presented which on one hand covers the process modeling for a set of dies and the required interconnects, on the other hand the test flow and the test cost for the complete stack. This tool is able to drastically reduce the effort of the system/process engineer in finding a feasible process and test flow.
